Method for avoiding cache misses during external tournament tree replacement sorting procedures
AssigneeInternational Business Machines Corporation
InventorsJames T. Brady, Balakrishna R. Iyer
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AssigneeInternational Business Machines Corporation
InventorsJames T. Brady, Balakrishna R. Iyer
Estimating the term…
A method and apparatus for avoiding line-accessed cache misses during a replacement/selection (tournament) sorting process. Prior to the sorting phase, the method includes the steps of sizing and writing maximal sets of sub-tree nodes of a nested ordering of keys, suitable for staging as cache lines. During the sort phase, the method includes the steps of prefetching into cache from CPU main memory one or more cache lines formed from a sub-tree of ancestor nodes immediate to the node in cache just selected for replacement. The combination of the clustering of ancestor nodes within individual cache lines and the prefetching of cache lines upon replacement node selection permits execution of the full tournament sort procedure without the normally-expected cache miss rate. For selection trees larger than those that can fit entirely into cache, the method avoids the second merge phase overhead that formerly doubled the sorting time necessary for larger cache sizes.
In a CPU having a main memory and a line-oriented cache coupled to said main memory, a method for generating sort strings of records while minimizing the number of cache reference misses per record, each said sort string being an ordering of keys of said records, said method including a selection tree having one or more sets of sub-tree nodes, said method comprising the steps of:
In a CPU having a main memory, a new use for a line-oriented cache coupling said memory for sort string generation of m records while minimizing the number of reference misses per record to said cache, said sort string generation being manifest as a nested ordering of keys of said records, comprising the steps of:
In a CPU having a main memory for storing program sequences and records, an LRU-managed cache coupling said memory, and means responsive to program sequences for accessing the contents of said main memory and said cache such that
In a data processing system for performing an external selection tree replacement sort of a plurality of records, said system having a main memory and a line-oriented cache coupled to said memory, said selection tree having one or more sets of sub-tree nodes, an apparatus for minimizing the number of cache reference misses per record during said sort, said apparatus comprising:
Dependencies are inferred from the claim text.