US 5,355,467 AGranted

Second level cache controller unit and system

AssigneeIntel Corporation

InventorsPeter D. MacWilliams, Robert L. Farrell, Adalberto Golbert, Itzik Silas

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Abstract

A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

Claims9

Dependent claims

A second level cache controller integrated circuit for use in a microprocessor system second level cache memory subsystem, the second level cache memory subsystem connected to a control processor unit (CPU) by means of a CPU bus and to a main memory bus for independently accessing a cache memory from the CPU bus and the main memory bus and for transferring data between the CPU bus and the main memory bus, the second level cache memory subsystem includes a memory bus controller for controlling access to and from the main memory bus, a cache memory coupled to the CPU bus and the main memory bus for data storage and retrieval, and a second level cache controller integrated circuit for control of the cache memory and independent data paths to and from the CPU bus and the main memory bus, the second level cache controller integrated circuit comprising:

a) a memory bus controller interface for coupling to the main memory bus controller and for adapting the second level cache controller to a specific main memory bus protocol;
b) a memory bus address queue coupled to the memory bus controller interface for scheduling main memory bus accesses by providing line and subline address data;
c) a CPU bus interface for coupling to the CPU bus and connected to the memory bus address queue for transmission of memory bus address data from the CPU bus to the memory bus address queue;
d) a cache memory interface for coupling to the secondary cache memory for control of the cache memory input and output cycles;
e) a memory bus interface for coupling to the main memory bus, for accepting and sending main memory bus addresses, and for performing snoop operations, connected to memory bus queue for acceptance of memory bus addresses originating from the CPU bus;
f) a cache directory array coupled to the memory bus interface for snoop addresses, coupled to the CPU bus interface for cache access addresses and having an output for coupling address information to the cache memory interface;
and
g) a snoop controller, selectably configurable for operation in a synchronous, an asynchronous, a strobed, and a clocked snoop mode, coupled to a second level cache controller clock, coupled to the main memory bus for receipt of snoop requests including snoop strobe and snoop clock signals, coupled to the memory bus interface for control of snoop address delivery to the cache directory array, coupled to the cache directory. array for delivering a snoop request and for receiving back a snoop request status signal, and coupled to the memory bus controller for communicating the snoop request status signal.

5 more elements

A second level cache memory system connected between a central processor (CPU) bus and a main memory bus, the CPU having a first level cache memory, the second level cache memory system comprising:

a) a cache memory subsystem with two independent cache data paths, one path coupled to the CPU bus and another coupled to the main memory bus, and a data path between the CPU bus and the main memory bus, operating synchronously with the CPU bus and asynchronously with the memory bus, controlled by a second level cache controller;
b) a second level cache controller integrated circuit comprising:
i) a memory bus controller interface for coupling to the main memory bus controller and for adapting the second level cache controller to a specific main memory bus protocol;
ii) a memory bus address queue coupled to the memory bus controller interface for scheduling main memory bus accesses by providing line and subline address data;
iii) a CPU bus interface for coupling to the CPU bus and connected to the memory bus address queue for transmission of memory bus address data from the CPU bus to the memory bus address queue;
iv) a cache memory interface for coupling to the secondary cache memory for control of the cache memory input and output cycles;
v) a memory bus interface for coupling to the main memory bus for accepting and sending main memory bus addresses, and for performing snoop operations, and connected to memory bus queue for acceptance of memory bus addresses originating from the CPU bus;
vi) a cache directory array coupled to the memory bus interface for snoop addresses, coupled to the CPU bus interface for cache access addresses and having an output for coupling address information to the cache memory interface;
and
vii) a snoop controller, configurable for a synchronous, an asynchronous, a strobed, and a clocked snoop mode, coupled to a second level cache controller clock, coupled to the main memory bus for receipt of snoop requests including snoop strobe and snoop clock signals, coupled to the memory bus interface for control of snoop address delivery to the cache directory array, coupled to the cache directory array for delivering a snoop request and for receiving back a snoop request status signal, and coupled to the memory bus controller for communicating the snoop request status signal;
and
c) a main memory bus controller, coupled to the main memory bus and cache controller for arbitrating and controlling access to the main memory bus using address data supplied by the second level cache controller for sending write data from the cache memory subsystem and for receiving data from the main memory bus.

9 more elements

Dependencies are inferred from the claim text.