# US 5,353,435 A · Microcomputer with circuit for generating multiple pulses each having different frequencies

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- Number: US 5,353,435 A
- Document ID: US5353435A
- Status: Granted
- Kind: A
- Application number: 07/864,999
- Filed: 1992-04-08
- Granted: 1994-10-04
- Earliest claimed: 1991-04-12
- Assignees: Mitsubishi Denki Kabushiki Kaisha
- Inventors: Hirokazu Kitagawa; Naoki Yamauchi
- Web page: https://patentgrep.com/patent/US5353435A

## CPC

- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In a microcomputer according to the present invention, output pulse levels are stored in bit coles corresponding to respective addresses of a memory circuit which are outputted from a timer circuit which uses a clock as a count source, and each bit output of the memory circuit is latched in synchronism with the clock and outputted to a port output circuit, so as to obtain a plurality of desired phase pulses having different cycles.

## Claims

### Claim 1

A microcomputer comprising:
a timer circuit having a clock as a count source;
a memory circuit to store output pulse waveforms represented as bit strings;
wherein said bit strings correspond to respective addresses output from said timer circuit;
a latch circuit to latch each bit read from said memory circuit in synchronism with said clock; and
a port output circuit to output each bit latched by said latch circuit to a corresponding port.

### Claim 2 (depends on 1)

A microcomputer according to claim 1, wherein said latch circuit and said port output circuit comprise a plurality of latches and a plurality of port outputs each of said latches and said port outputs associated with an individual one of said bit strings, respectively.

### Claim 3 (depends on 1)

A microcomputer according to claim 1, wherein said timer circuit further comprises a reload register.

### Claim 4 (depends on 1)

A microcomputer according to claim 1, wherein said memory circuit is a ROM circuit.