# US 5,353,431 A · Memory address decoder with storage for memory attribute information > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,353,431 A - Document ID: US5353431A - Status: Granted - Kind: A - Application number: 08/193,516 - Filed: 1994-02-08 - Granted: 1994-10-04 - Earliest claimed: 1991-04-29 - Assignees: Intel Corporation - Inventors: Patrick F. Doyle; Leonard W. Cross; Roger Noar - Web page: https://patentgrep.com/patent/US5353431A ## CPC - G06F 12/0684: {with feedback, e.g. presence or absence of unit detected by addressing, overflow detection} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The memory address decoder includes an SRAM for storing a memory map which associates memory attributes with memory ranges or blocks of memory. The memory attributes include: memory residence, caching, write protection of memory ranges, and the decoding of other memory modules. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode. A default power up mode is entered after power is first applied to the computer system. When the processor specifies a programming mode, the processor may write data directly into the SRAM. When the processor specifies the read back mode, the contents of the SRAM may be read back by the processor through the read back register. A normal mode may be entered in order to enable access to system memory (DRAM) with memory attribute information. ## Claims ### Claim 1 An improved memory address decoder comprising: means for receiving addressing signals; memory means for storing a Software programmable memory map, said memory means coupled to said receiving means, said memory map for storing memory attribute information associated with said addressing signals received by said receiving means, said memory attribute information for defining at least one state of a plurality of memory attributes associated with a corresponding block of system memory indicated by said addressing signals; control logic coupled to said memory means for controlling access to said memory means and controlling an output of said memory attribute information from said memory means, said control logic further including means for programming said software programmable memory map according to at least one processor instruction; and means for outputting said memory attribute information, said means for outputting coupled to said memory means. ### Claim 2 (depends on 1) The improved memory address decoder as claimed in claim 1 further including means for reading the content of said memory means, said means for reading coupled to said memory means. ### Claim 3 (depends on 2) The improved memory address decoder as claimed in claim 2 wherein said means for reading further including a read-back register for storing the content of a location in said memory means while said location is being read. ### Claim 4 (depends on 2) The improved memory address decoder as claimed in claim 2 further including: means for receiving mode information; and a mode register coupled to said means for receiving mode information and said control logic, said mode register for storing mode information received by said means for receiving mode information, said mode information read by said control logic, said means for reading the contents of said memory means activated when said mode information indicates a read back mode. ### Claim 5 (depends on 1) The improved memory address decoder as claimed in claim 1 further including: means for receiving mode information; and a mode register coupled to said means for receiving mode information and said control logic, said mode register for storing mode information received by said means for receiving mode information, said mode information read by said control logic. ### Claim 6 (depends on 5) The improved memory address decoder as claimed in claim 5 wherein said control logic further includes means for disabling the output of said memory attribute information from said memory means, said means for disabling being activated when said mode information indicates a power-up mode. ### Claim 7 (depends on 4) The improved memory address decoder as claimed in claim 4 wherein said means for programming is activated when said mode information indicates a programming mode. ### Claim 8 (depends on 5) The improved memory address decoder as claimed in claim 5 wherein said control logic further includes means for enabling the output of said memory attribute information from said memory means, said means for enabling being activated when said mode information indicates a normal operation mode. ### Claim 9 (depends on 1) The improved memory address decoder as claimed in claim 1 further including non-volatile memory means for storing processing logic and memory configuration data. ### Claim 10 (depends on 1) The improved memory address decoder as claimed in claim 1 wherein said memory means is a static random access memory device. ### Claim 11 (depends on 1) The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes memory residence information. ### Claim 12 (depends on 1) The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes write protection information. ### Claim 13 (depends on 1) The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes internal cache information. ### Claim 14 (depends on 1) The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes external cache information. ### Claim 15 (depends on 1) The improved memory address decoder as claimed in claim 1 wherein said plurality of memory attributes includes memory module configuration information. ### Claim 16 A process for decoding addressing signals, said process comprising the steps of: receiving addressing signals; accessing a software programmable memory map stored in a memory means, said memory map for storing memory attribute information associated with said addressing signals received in said receiving step, said memory attribute information for defining at least one state of a plurality of memory attributes associated with a corresponding block of system memory indicated by said addressing signals; reading a mode register to determine mode information; programming said software programmable memory map according to at least one processor instruction when said mode information indicates a programming mode; and outputting said memory attribute information when indicated by said mode information. ### Claim 17 (depends on 16) The process as claimed in claim 16 further including a step of reading the contents of said memory means when said mode information indicates a read-back mode. ### Claim 18 (depends on 16) The process as claimed in claim 16 further including a step of reading processing logic and memory configuration data stored in a non-volatile memory means. ### Claim 19 (depends on 16) The process as claimed in claim 16 wherein said accessing step further includes a step of reading memory residence information stored in said memory means. ### Claim 20 (depends on 16) The process as claimed in claim 16 wherein said accessing step further includes a step of reading write protection information stored in said memory means. ### Claim 21 (depends on 16) The process as claimed in claim 16 wherein said accessing step further includes a step of reading internal cache information stored in said memory means. ### Claim 22 (depends on 16) The process as claimed in claim 16 wherein said accessing step further includes a step of reading external cache information stored in said memory means. ### Claim 23 (depends on 16) The process as claimed in claim 16 wherein said accessing step further includes a step of reading memory module configuration information stored in said memory means. ### Claim 24 (depends on 16) The process as claimed in claim 16 wherein said outputting step further includes a step of disabling the output of said memory attribute information when said mode information indicates a power-up mode. ### Claim 25 (depends on 16) The process as claimed in claim 16 wherein said outputting step further includes a step of enabling the output of said memory attribute information when said mode information indicates a normal operation mode.