# US 5,353,420 A · Method and apparatus for decoding conditional jump instructions in a single clock in a computer processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,353,420 A - Document ID: US5353420A - Status: Granted - Kind: A - Application number: 07/927,707 - Filed: 1992-08-10 - Granted: 1994-10-04 - Earliest claimed: 1992-08-10 - Assignees: Intel Corporation - Inventors: Syed A. A. Zaidi - Web page: https://patentgrep.com/patent/US5353420A ## CPC - G06F 9/382: {Pipelined decoding, e.g. using predecoding} - G06F 9/30149: {of variable length instructions} - G06F 9/3017: {Runtime instruction translation, e.g. macros} - G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode} - G06F 9/3822: {Parallel decoding, e.g. parallel decode units} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed; a decode unit having a prefix state machine for decoding prefixes and determining their lengths, a decode circuit for decoding instructions and generating microcode vectors to be executed, and apparatus for counting the length of an instruction; and a microcontroller for sequencing microcode vectors; the improvement including apparatus for detecting the appearance of a particular prefixed instruction, apparatus responsive to the detection of the particular prefixed instruction for disabling the prefix state machine, apparatus in the decode circuit for decoding the particular prefixed instruction and causing the decode circuit to generate microcode vectors for the instruction, and apparatus for generating a request to the microcontroller to handle microcode vectors generated. ## Claims ### Claim 1 In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed; a decode unit having a prefix state machine for decoding prefixes to instructions and determining their lengths, a decode circuit for decoding instructions and generating microcode vectors to be executed, the decode circuit being responsive to signals from the prefix state machine to vary the microcode vector generated, and means for counting the length of an instruction; and a microcontroller for sequencing microcode vectors; the improvement comprising: means for detecting the appearance of a particular prefixed instruction, means responsive to the detection of the particular prefixed instruction for disabling the prefix state machine, means in the decode circuit for decoding the particular prefixed instruction and causing the decode circuit to generate microcode vectors for the instruction, and means for generating a request to the microcontroller for microcode vectors generated. ### Claim 2 (depends on 1) In a pipelined microprocessor as claimed in claim 1, the improvement further comprising means for causing the means for counting to include the length of a prefix in any length counted for the particular prefixed instruction. ### Claim 3 (depends on 2) In a pipelined microprocessor as claimed in claim 2, the means for causing the means for counting to include the length of a prefix in any length counted for the particular prefixed instruction comprising means for generating a signal in response to the detection of the particular prefixed instruction for increasing the length count. ### Claim 4 (depends on 3) In a pipelined microprocessor as claimed in claim 3, the improvement further comprising means for utilizing the signal generated in response to the detection of the particular prefixed instruction for increasing the length count to indicate that a byte of instruction exists in an unused field of an instruction being processed. ### Claim 5 (depends on 3) In a pipelined microprocessor as claimed in claim 3, the improvement further comprising means for utilizing a count of the length of an instruction to indicate the length of the instruction to remaining stages in the pipeline. ### Claim 6 (depends on 3) In a pipelined microprocessor as claimed in claim 3, the improvement further comprising means for utilizing a count of the length of an instruction to indicate the length of the instruction to a prefetch unit. ### Claim 7 (depends on 3) In a pipelined microprocessor as claimed in claim 3, the improvement further comprising means for increasing a count value for the opcode in order to provide correct extraction of another field of the instruction. ### Claim 8 The method of decoding a prefixed jump instruction in a single clock period in an Intel microprocessor having a state machine for detecting and decoding prefixes apart from the decoding of instructions of which they are a part in a decoder circuit, the decoder circuit normally generating a count of the bytes of the instruction not including any prefix bytes for generating a prefetch pointer, comprising the steps of detecting the presence of a prefixed jump instruction, disabling the state machine in response to the detection of the prefixed jump instruction, decoding the prefixed jump instruction in the decoder circuit, generating a microcode vector for the decoded prefixed jump instruction, and increasing the count of the number of bytes in the decoded instruction by one byte. ### Claim 9 (depends on 8) The method of decoding a prefixed jump instruction in a single clock period in an Intel microprocessor as claimed in claim 8 in which the step of increasing the count of the number of bytes in the decoded instruction by one byte comprises the step of providing a signal in response to the detection of the prefixed jump instruction to indiacate that a byte of instruction exists in an unused field of the decoded instruction, and counting the byte of instruction in the unused field of the decoded instruction in determining the count of the number of bytes in the decoded instruction. ### Claim 10 (depends on 8) The method of decoding a prefixed jump instruction in a single clock period in an Intel microprocessor as claimed in claim 8 in which the unused field of the decoded instruction is the immediate field.