# US 5,353,353 A · Repeater security system

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- Number: US 5,353,353 A
- Document ID: US5353353A
- Status: Granted
- Kind: A
- Application number: 08/053,797
- Filed: 1993-04-26
- Granted: 1994-10-04
- Earliest claimed: 1993-04-26
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Nader Vijeh; William Lo
- Web page: https://patentgrep.com/patent/US5353353A

## CPC

- H04L 63/0227: {Filtering policies (mail message filtering H04L51/212)}
- H04L 12/22: Arrangements for preventing the taking of data from a data transmission channel without authorisation (means for verifying the identity or the authority of a user of a secure or secret communication system H04L9/32)
- H04L 12/44: Star or tree networks
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A system is provided for use in a network providing security to ensure the prevention of unauthorized receipt of data. The system utilizes a jamming sequence to prevent unauthorized ports from receiving certain data. Repeaters utilized in the network are provided with the capability to detect a particular data sequence to provide the improved features.

## Claims

### Claim 1

A system for providing security for a network that includes a plurality of ports for transmitting and receiving data, the data including a bit that indicates the start of a data stream and a bit corresponding to each port that is to receive the data the system comprising;
a plurality of disrupt circuits means coupled to the plurality of ports, there being one disrupt circuit means for each port, each of the disrupt means being coupled in a serial fashion;
a detect circuit means coupled between a first disrupt circuit means and a last disrupt circuit means to detect when the start bit has reached to last disrupt circuit means; and
means for providing a jam sequence of data that will block a data bitstream from reaching a particular port responsive to the detect circuit means.

### Claim 2 (depends on 1)

The system of claim 1 in which each of the disrupt circuit means includes a shift register, each of the shift registers being chained in a serial manner.

### Claim 3 (depends on 2)

The system of claim 2 in which each of the disrupt circuit means includes a latch for receiving a bit of from the data bitstream which provides an indication of whether the data provided to a particular port should be disrupted.

### Claim 4 (depends on 3)

The system of claim 3 in which each of the latches correspond to each of the ports.

### Claim 5 (depends on 4)

The system of claim 4 in which the detect circuit means comprises;
means for detecting a start bit;
means coupled to the detecting means for determining whether the start bit has reached to one bit shift register; and
means responsive to the start bit reaching the last one bit shift register for asserting a signal that latches bits from the plurality of one bit shift register to the latch to indicate whether a port should be disrupted.

### Claim 6 (depends on 5)

The system of claim 5 in which the asserting means provides a strobe signal to the one bit shift registers that latches the data into the latches.