# US 5,353,308 A · Event qualified test methods and circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,353,308 A - Document ID: US5353308A - Status: Granted - Kind: A - Application number: 08/134,510 - Filed: 1993-10-08 - Granted: 1994-10-04 - Earliest claimed: 1990-08-06 - Assignees: Texas Instruments Incorporated - Inventors: Lee D. Whetsel, Jr. - Web page: https://patentgrep.com/patent/US5353308A ## CPC - G01R 31/318555: {Control logic} - G06F 11/2273: {Test methods} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An event qualification architecture comprises event qualification cells (24) having an internal memory for detecting qualification events. The event qualification cells (24) output a signal indicating when a match has occurred, which is interpreted by an event qualification module (22). The event qualification module controls the test circuitry which may include test cell registers (14, 16) and test memory (28). A number of protocols are provided which can be designed into a circuit to provide the timing and control required to activate test logic in the circuit during normal system operation. ## Claims ### Claim 1 A method of testing a circuit comprising the steps of: providing at least one event qualification cell having an internal memory and having compare circuitry for comparing data input into the compare circuitry with data stored in said internal memory; operating said event qualification cell for detecting each occurrence of a specified event; counting the number of occurrences of the specified event; executing a test responsive to detecting a predetermined number of occurrences of the specified event; and executing said test for a predetermined number of clocks. ### Claim 2 (depends on 1) The method of claim 1 and further comprising the step of repeating said counting and executing steps a predetermined number of times wherein the predetermined number of occurrences of the specified event may vary on each repetition. ### Claim 3 (depends on 1) The method of claim 1 and further comprising the steps of: detecting a second specified event; counting the number of occurrences of the second specified event; and stopping the test responsive to detection of a predetermined number of occurrences of the second specified event. ### Claim 4 (depends on 3) The method of claim 3 and further comprising the step of repeating a predetermined number of times said steps of counting the number of occurrences of the first specified event, executing a test, counting the number of occurrences of the second specified event and stopping the test wherein the predetermined number of occurrences of the first specified event and the predetermined number of occurrences second specified event may vary on each repetition. ### Claim 5 (depends on 3) The method of claim 3 wherein said stopping test step comprises the step of stopping the test responsive to detecting a predetermined number of clock cycles after a predetermined number of occurrences of the second specified event. ### Claim 6 (depends on 5) The method of claim 5 and further comprising the step of repeating a predetermined number of times said steps of counting the number of occurrences of the first event, executing a test responsive to detection of a predetermined number of occurrences of the first event, counting the number of occurrences of the second event, and stopping the test after detection of a predetermined number of occurrences of the second event wherein the predetermined number of occurrences of the first specified event, the predetermined number of clock cycles and the predetermined number of occurrences of the second specified event may vary on each repetition. ### Claim 7 (depends on 5) The method of claim 5 wherein said step of starting the test comprises the steps of pausing a predetermined number of clock cycles after detecting the predetermined number of occurrences of said first event and executing the test after pausing. ### Claim 8 (depends on 7) The method of claim 7 and further comprising the step of repeating a predetermined number of times said steps of counting the number of occurrences of the first event, pausing a predetermined number of clock cycles after detection of a predetermined number of occurrences of the first event, executing the test after pausing, counting the number of occurrences of the second event, and stopping the test after detection of a predetermined number of occurrences of the second event wherein the predetermined number of occurrences of the first specified event, predetermined number of occurrences of the second specified event, predetermined number of pausing clock cycles and predetermined number of clock cycles after detecting said first event may vary on each repetition. ### Claim 9 (depends on 1) The method of claim 1 wherein said executing step comprises the step of executing the test for a predetermined number of clock cycles and further comprising the steps of pausing the test for a predetermined number of clocks and resuming the test for a predetermined number of clocks. ### Claim 10 (depends on 9) The method of claim 9 and further comprising the step of repeating said pausing and resuming steps a predetermined number of times wherein the predetermined number of clocks for pausing and predetermined clocks for resuming may vary on each repetition. ### Claim 11 (depends on 1) The method of claim 1 wherein said executing step comprises the step of pausing a predetermined number of clock cycles after detecting a predetermined number of occurrences of the specified event and executing the test after pausing. ### Claim 12 (depends on 11) The method of claim 11 and further comprising the step of stopping the test after detecting a predetermined number of second events. ### Claim 13 (depends on 12) The method of claim 12 and further comprising the step of repeating said counting, executing and stopping steps a predetermined number of times wherein the predetermined number of occurrences of said first event, said predetermined number of occurrences of said second event and predetermined number of clocks may vary on each repetition. ### Claim 14 (depends on 1) The method of claim 1 and further comprising the step of repeating said counting, pausing and executing steps a predetermined number of times. ### Claim 15 (depends on 1) The method of claim 1 wherein said executing step comprises the step of pausing for a predetermined number of clocks and executing the test for a predetermined number of clocks after said pausing step. ### Claim 16 (depends on 15) The method of claim 15 and further comprising the step of repeating said counting, pausing and executing steps for a predetermined number of times wherein said predetermined number of occurrences of the specified event, predetermined number of clocks to pause and predetermined number of clocks to test may vary on each repetition. ### Claim 17 (depends on 1) The method of claim 1 and further comprising the step of repeating said counting and executing steps a predetermined number of times wherein said predetermined number of occurrences of the specified event and predetermined number of clocks may vary on each repetition. ### Claim 18 (depends on 1) The method of claim 1 wherein said executing step comprises the steps of pausing a predetermined number of clocks and executing the test a predetermined number of clocks. ### Claim 19 (depends on 18) The method of claim 18 and further comprising the step of repeating said pausing and executing steps a predetermined number of times wherein said predetermined number of clocks for pausing and predetermined number of clocks for testing may vary on each repetition. ### Claim 20 A method of testing a circuit comprising the steps of: providing at least one event qualification cell having an internal memory and having compare circuitry for comparing data input into the compare circuitry with data stored in said internal memory; operating said event qualification cell for detecting each occurrence of a specified event; counting the number of occurrences of the specified event; executing a test for a predetermined number of clocks during a predetermined occurrence of the event. ### Claim 21 (depends on 20) The method of claim 20 and further comprising the step of repeating said counting and executing steps a predetermined number of times wherein said predetermined number of occurrences of the specified event may vary on each repetition. ### Claim 22 Circuitry for testing a circuit comprising: at least one event qualification cell having an internal memory and having compare circuitry for comparing data input into the compare circuitry with data stored in said internal memory, operable for detecting each occurrence of a specified event; circuitry for counting the number of occurrences of the specified event; circuitry for executing a test responsive to detecting a predetermined number of occurrences of the specified event; and circuitry for causing said test to execute for a predetermined number of clocks. ### Claim 23 (depends on 22) The circuitry of claim 22 and further comprising circuitry for repeating said test a predetermined number of times. ### Claim 24 (depends on 22) The circuitry of claim 22 and further comprising: circuitry for detecting a second specified event; circuitry for counting the number of occurrences of the second specified event; and circuitry for stopping the test responsive to detection of a predetermined number of occurrences of the second specified event. ### Claim 25 (depends on 24) The circuitry of claim 24 and further comprising circuitry for repeating said test a predetermined number of times responsive to said counting circuitry and said stopping circuitry. ### Claim 26 (depends on 24) The circuitry of claim 24 wherein said circuitry for stopping comprises circuitry for stopping the test a predetermined number of clock cycles after a predetermined number of occurrences of the second specified event. ### Claim 27 (depends on 26) The circuitry of claim 26 and further comprising circuitry for repeating said test a predetermined number of times responsive to said circuitry for counting the number of occurrences of the first event, circuitry for counting the number of occurrences of the second event, and circuitry for stopping the test after detection of a predetermined number of occurrences of the second event. ### Claim 28 (depends on 26) The circuitry of claim 26 wherein said circuitry for starting the test comprises circuitry for pausing a predetermined number of clock cycles after detecting the predetermined number of occurrences of said first event and circuitry for executing the test after pausing. ### Claim 29 (depends on 28) The circuitry of claim 28 and further comprising circuitry for repeating the test a predetermined number of times responsive to said circuitry for counting the number of occurrences of the first event, circuitry for pausing, circuitry for executing the test after pausing, circuitry for counting the number of occurrences of the second event, and circuitry for stopping the test after detection of a predetermined number of occurrences of the second event. ### Claim 30 (depends on 22) The circuitry of claim 22 wherein said executing circuitry comprises circuitry for executing the test for a predetermined number of clock cycles and further comprising circuitry for pausing for a predetermined number of clocks and resuming the test for a predetermined number of clocks. ### Claim 31 (depends on 30) The circuitry of claim 30 and further comprising circuitry for continuing the test responsive to said circuitry for pausing and circuitry for resuming. ### Claim 32 (depends on 22) The circuitry of claim 22 wherein said circuitry for executing comprises circuitry for pausing a predetermined number of clock cycles after detecting a predetermined number of occurrences of the specified event and executing the test after pausing. ### Claim 33 (depends on 32) The circuitry of claim 32 and further comprising circuitry for stopping the test after detecting predetermined number of second events. ### Claim 34 (depends on 33) The circuitry of claim 33 and further comprising circuitry for repeating the test responsive to said circuitry for counting, circuitry for executing and circuitry for stopping. ### Claim 35 (depends on 32) The circuitry of claim 32 and further comprising circuitry for repeating the test responsive to said circuitry for counting, circuitry for pausing and circuitry for executing. ### Claim 36 (depends on 22) The circuitry of claim 22 wherein said circuitry for executing comprises circuitry for pausing for a predetermined number of clocks and executing the test for a predetermined number of clocks after pausing. ### Claim 37 (depends on 36) The circuitry of claim 36 and further comprising circuitry for repeating the test responsive to said circuitry for counting, circuitry for pausing and circuitry for executing. ### Claim 38 (depends on 32) The circuitry of claim 32 and further comprising circuitry for repeating the test responsive to said circuitry for counting and circuitry for executing. ### Claim 39 (depends on 22) The circuitry of claim 22 wherein said circuitry for executing comprises circuitry for pausing a predetermined number of clocks and circuitry for executing the test for a predetermined number of clocks. ### Claim 40 (depends on 39) The circuitry of claim 39 and further comprising circuitry for continuing the test responsive to said circuitry for pausing and circuitry for executing. ### Claim 41 Circuitry for testing a circuit comprising: at least one event qualification cell having an internal memory and having compare circuitry for comparing data input into the compare circuitry with data stored in said internal memory, operable for detecting each occurrence of a specified event; circuitry for counting the number of occurrences of the specified event; and circuitry for executing a test for a predetermined number of clocks during a predetermined occurrence of the event. ### Claim 42 (depends on 41) The circuitry of claim 41 and further comprising circuitry for repeating the test responsive to said circuitry for counting and circuitry for executing.