# US 5,353,284 A · Data transmission system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,353,284 A - Document ID: US5353284A - Status: Granted - Kind: A - Application number: 07/973,916 - Filed: 1992-11-12 - Granted: 1994-10-04 - Earliest claimed: 1991-11-12 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Yasuhisa Shiobara - Web page: https://patentgrep.com/patent/US5353284A ## CPC - G06F 13/128: {for dedicated transfers to a network (for protocol converters G06F13/387)} - H04L 9/40: Network security protocols - H04L 12/28: characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] (wireless communication networks H04W {; arrangements for dividing the transmission path H04W40/00}) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A data transmission system has multiple nodes connected to a common transmission medium. Each of the multiple nodes transmits data and the other nodes receive and store the data through the common transmission medium. The received data is read out for information exchange among the nodes. The node has transceiver circuitry for receiving a data frame and transmitting the data frame, receive and transmission control circuitry, receive data frame transmission control circuitry, a receive buffer, an external interface and address conversion memory circuitry. The receive and transmission control circuitry receives a data frame from the transceiver, detects whether or not the data frame designates that node and is received without errors, and transmits a data frame reception start signal and a data frame reception end signal. The data frame transmission control circuitry extracts predetermined received data included in the received data frame in response to the data frame reception start signal, and transmits the predetermined received data in response to the data frame reception end signal. The receive buffer receives and stores the predetermined received data, and the external interface provides a specific address. The address conversion memory circuitry stores an address of the received data stored in the receive buffer and converts the specific address into the address of the received data, thereby generating a conversion address. This considerably shortens the time required to transmit the received data, and improves data transmission speed in the whole system. ## Claims ### Claim 1 A data transmission system comprising: a plurality of nodes connected to a common transmission medium, the nodes periodically transmitting, receiving and storing data, wherein data received at one of the nodes is read out using a specific address common among the plurality of nodes for information exchange, each node further comprising: a transceiver connected to the common transmission medium, the transceiver receiving a data frame and transmitting the data frame; receive and transmission control means, the receive and transmission control means receiving the data frame, detecting whether the data frame designates said node and thereafter transmitting a data frame reception start signal and a data frame reception end signal; received data frame transmission control means, the received data frame transmission control means extracting received data included in the received data frame in response to the data frame reception start signal, and transmitting the received data in response to the data frame reception end signal; a receive buffer, receiving and storing the received data; an interface providing the specific address; an address conversion memory means, the address conversion memory means storing an address of the received data in the receive buffer and generating a conversion address in order to convert the specific address from the interface into the address of the received data and access the received data. ### Claim 2 (depends on 1) A data transmission system according to claim 1, wherein: the receive buffer has multiple blocks divided in accordance with the number of data included in the data frame, the number of the blocks being at least one more than a total number of data frames to be received, the receive and transmission control means transmits a normal data frame reception end signal indicating the data frame is received normally and an abnormal data frame reception end signal indicating the data frame is received abnormally, the received data frame transmission control means has means for transmitting received data to an empty one of the blocks in the receive buffer as a received data frame is detected to be a data frame in response to a data frame reception start signal of the data frame, and the receive and transmission control means further rewrites an address in the receive buffer, thereby storing received data corresponding to the specific address in the address conversion memory to an address in a block in the receive buffer in order to regard the block as new received data for the external interface in response to the normal data frame reception end signal. ### Claim 3 (depends on 2) The apparatus recited in claim 2, wherein, in response to receipt of the abnormal data frame reception end signal, the contents of the address conversion memory is prevented from renewing and the block is renewed in order to write next received data. ### Claim 4 (depends on 1) The apparatus recited in claim 1, wherein said address conversion memory means comprises: a dual port memory, the dual port memory storing top addresses of memory blocks in the receive buffer; and an adder having a first input receiving the specific address from the interface, a second input from the dual port memory and an output, the output being the conversion address to access the received data. ### Claim 5 (depends on 1) The apparatus recited in claim 1, wherein the receive and transmission control means comprises means for determining whether the data frame is received without errors. ### Claim 6 (depends on 1) The apparatus recited in claim 1 wherein the address conversion memory means comprises a memory initialized with the addresses of the receive buffer where the received data is received. ### Claim 7 A method of data transmission among interconnected nodes, the method comprising the steps of: receiving at one of the nodes a data frame transmitted on a transmission medium; detecting whether said data frame designates said node and thereafter transmitting a data frame reception start signal and data frame reception end signal; extracting received data in said data frame in response to said data frame reception start signal and transmitting the received data; receiving and storing the received data at an address in a receive buffer; receiving into an external interface from host equipment a specific address; storing the address of the received data in the receive buffer in an address conversion memory and generating a conversion address to convert the specific address received by the external interface into the address of the received data. ### Claim 8 (depends on 7) The method recited in claim 7, further comprising the steps of: storing in a dual port memory top addresses of memory blocks in the receive buffer; and adding the specific address to the top address corresponding to one of the blocks in the dual port memory, thereby generating the conversion address to access data in the receive buffer. ### Claim 9 (depends on 8) The method recited in claim 8 further comprising the step of downloading top addresses into the dual port memory at an initialization time. ### Claim 10 (depends on 8) The method recited in claim 8 further comprising the step of detecting whether the data frame is received without errors.