# US 5,353,257 A · Word line driving circuit and semiconductor memory device using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,353,257 A - Document ID: US5353257A - Status: Granted - Kind: A - Application number: 08/016,613 - Filed: 1993-02-11 - Granted: 1994-10-04 - Earliest claimed: 1992-02-17 - Assignees: Fujitsu Limited - Inventors: Makoto Yanagisawa; Yukinori Kodama - Web page: https://patentgrep.com/patent/US5353257A ## CPC - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In a word line driving circuit coupled to a word line of a memory cell array of a semiconductor memory device, a first transistor has a first terminal receiving an input signal based on a row address signal applied to the semiconductor memory device, a second terminal, and a control terminal receiving a first timing signal. A second transistor having a first terminal receiving a second timing signal, a second terminal connected to the word line, and a control terminal connected to the second terminal of the first transistor. A third transistor has a first terminal connected to the second terminal of the second transistor, a second terminal set at a predetermined potential, and a control terminal receiving a third timing signal. The first transistor has a threshold voltage less than that of at least one of the second and third transistors. ## Claims ### Claim 1 A word line driving circuit coupled to a word line of a memory cell array of a semiconductor memory device, said word line driving circuit comprising: a first transistor having a first terminal receiving an input signal based on a row address signal applied to the semiconductor memory device; a second terminal, and a control terminal receiving a first timing signal; a second transistor having a first terminal receiving a second timing signal, a second terminal connected to the word line, and a control terminal connected to the second terminal of the first transistor; and a third transistor having a first terminal connected to the second terminal of the second transistor, a second terminal set at a predetermined potential, and a control terminal receiving a third timing signal, the first transistor having a threshold voltage less than that of the third transistor. ### Claim 2 (depends on 1) The word line driving circuit as claimed in claim 1, wherein the first transistor has an impurity concentration less than that of said at least one of the second and third transistors. ### Claim 3 (depends on 1) The word line driving circuit as claimed in claim 1, wherein the first timing signal is fixed at a power supply voltage applied to the semiconductor memory device. ### Claim 4 (depends on 1) The word line driving circuit as claimed in claim 1, wherein the threshold voltage of the first transistor is less than that of the second transistor. ### Claim 5 (depends on 1) The word line driving circuit as claimed in claim 1, wherein the threshold voltage of the first transistor is less than threshold voltages of the second and third transistors. ### Claim 6 (depends on 1) The word line driving circuit as claimed in claim 1, wherein the third timing signal is an inverted version of the input signal. ### Claim 7 (depends on 1) The word line driving circuit as claimed in claim 1, wherein the second timing signal is at a potential at which the first timing signal is, when both the first and second timing signals are high. ### Claim 8 (depends on 1) The word line driving circuit as claimed in claim 1, wherein the first, second and third transistors are n-channel field effect transistors. ### Claim 9 A semiconductor memory device comprising: a memory cell array connected to word lines and bit lines; a row address decoder selecting one of the word lines in response to a row address signal; a column address decoder selecting one of the bit lines in response to a column address signal; and data input/output means, coupled to the memory cell array, for writing data into the memory cell array and reading data from the memory cell array, said row address decoder comprising word line driving circuits respectively provided for the word lines, each of the word line driving circuits comprising: a first transistor having a first terminal receiving an input signal based on the row address signal, a second terminal, and a control terminal receiving a first timing signal; a second transistor having a first terminal receiving a second timing signal, a second terminal connected to the word line, and a control terminal connected to the second terminal of the first transistor; and a third transistor having a first terminal connected to the second terminal of the second transistor, a second terminal set at a predetermined potential, and a control terminal receiving a third timing signal, the first transistor having a threshold voltage less than that of the third transistor. ### Claim 10 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein the first transistor has an impurity concentration less than that of said at least one of the second and third transistors. ### Claim 11 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein the first timing signal is at a fixed potential equal to a power supply voltage applied to the semiconductor memory device. ### Claim 12 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein the threshold voltage of the first transistor is less than that of the second transistor. ### Claim 13 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein the threshold voltage of the first transistor is less than threshold voltages of the second and third transistors. ### Claim 14 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein the third timing signal is an inverted version of the input signal. ### Claim 15 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein the second timing signal is at a potential at which the first timing signal is, when both the first and second timing signals are high. ### Claim 16 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein the first, second and third transistors are n-channel field effect transistors. ### Claim 17 (depends on 9) The semiconductor memory device as claimed in claim 9, wherein said semiconductor memory device is a dynamic random access memory device.