# US 5,353,251 A · Memory cell circuit with single bit line latch

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,353,251 A
- Document ID: US5353251A
- Status: Granted
- Kind: A
- Application number: 08/123,434
- Filed: 1993-09-16
- Granted: 1994-10-04
- Earliest claimed: 1992-09-21
- Assignees: Sharp Kabushiki Kaisha
- Inventors: Munehiro Uratani; Aoi Kitaura
- Web page: https://patentgrep.com/patent/US5353251A

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 11/412: using field-effect transistors only
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory cell circuit for a CMOS static RAM is provided, which includes a latch portion for holding logic high or logic low data depending on the potential of a single bit line, and a transfer gate having a first terminal connected to the latch portion and a second terminal connected to the single bit line, the transfer gate electrically connecting or disconnecting the first and second terminals in response to a selection signal, wherein the transfer gate includes a first transistor and a second transistor connected in parallel between the first and second terminals, both of the first and second transistors being activated at a data write operation, while one of the first and second transistors being activated at a data read operation.

## Claims

### Claim 1

A memory cell circuit comprising:
latch means for holding logic high or logic low data depending on the potential of a single bit line; and
transfer gate means having a first terminal connected to said latch means and a second terminal connected to said single bit line, said transfer gate means electrically connecting or disconnecting said first terminal and said second terminal in response to a selection signal,
wherein said transfer gate means includes a first transistor and a second transistor connected in parallel between said first terminal and said second terminal, both of said first transistor and said second transistor being activated during a data write operation, while one of said first transistor and said second transistor being activated during a data read operation.

### Claim 2 (depends on 1)

A memory cell circuit according to claim 1, wherein a gate terminal of said first transistor is connected to a first word line conveying a first selection signal, and a gate terminal of said second transistor is connected to a second word line conveying a second selection signal.

### Claim 3 (depends on 2)

A memory cell circuit according to claim 2, wherein said second line is connected to an output terminal of a control element for controlling the potential of said second word line, and said control element outputs to said output terminal a signal inverted from said first selection signal as said second selection signal during said data write operation, while said control element outputs to said output terminal a signal not inverted from said first selection signal as said second selection signal during said data read operation.

### Claim 4 (depends on 3)

A memory cell circuit according to claim 3, wherein said control element is an NAND element including a first input terminal for receiving a signal indicating the mode of said data write operation or said data read operation and a second input terminal connected to said first word line.

### Claim 5 (depends on 4)

A memory cell circuit according to claim 4, wherein said first transistor is a first n-channel MOS transistor, and said second transistor is a first p-channel MOS transistor.

### Claim 6 (depends on 5)

A memory cell circuit according to claim 5, wherein said latch means includes a first inverter and a second inverter, an input terminal of said first inverter and an output terminal of said second inverter are connected with each other, an input terminal of said second inverter and an output terminal of said first inverter are connected with each other, and said output terminal of said first inverter is connected with said first terminal of said transfer gate.

### Claim 7 (depends on 6)

A memory cell circuit according to claim 6, wherein said first inverter includes a second p-channel MOS transistor disposed between said output terminal of said first inverter and a high-potential source and a second n-channel MOS transistor disposed between said output terminal and a low-potential source, and said second inverter includes a third p-channel MOS transistor disposed between said output terminal of said second inverter and said high-potential source and a third n-channel MOS transistor disposed between said output terminal and said low-potential source.

### Claim 8 (depends on 7)

A memory cell circuit according to claim 7, wherein said high-potential source is a power source supplying a logic high potential, and said low-potential source is a power source supplying a logic low potential.

### Claim 9 (depends on 6)

A memory cell circuit according to claim 6, wherein said first inverter includes a first resistance disposed between said output terminal of said first inverter and a high-potential source and a second n-channel MOS transistor disposed between said output terminal and a low-potential source, and said second inverter includes a second resistance disposed between said output terminal of said second inverter and said high-potential source and a third n-channel MOS transistor disposed between said output terminal and said low-potential source.

### Claim 10 (depends on 9)

A memory cell circuit according to claim 9, wherein said high-potential source is a power source supplying a logic high potential, and said low-potential source is a power source supplying a logic low potential.

### Claim 11 (depends on 1)

A memory cell circuit according to claim 1, wherein said latch means includes a first inverter and a second inverter, an input terminal of said first inverter and an output terminal of said second inverter are connected with each other, an input terminal of said second inverter and an output terminal of said first inverter are connected with each other, and said output terminal of said first inverter is connected with said first terminal of said transfer gate.

### Claim 12 (depends on 11)

A memory cell circuit according to claim 11, wherein said first inverter includes a second p-channel MOS transistor disposed between said output terminal of said first inverter and a high-potential source and a second n-channel MOS transistor disposed between said output terminal and a low-potential source, and said second inverter includes a third p-channel MOS transistor disposed between said output terminal of said second inverter and said high-potential source and a third n-channel MOS transistor disposed between said output terminal and said low-potential source.

### Claim 13 (depends on 12)

A memory cell circuit according to claim 12, wherein said high-potential source is a power source supplying a logic high potential, and said low-potential source is a power source supplying a logic low potential.

### Claim 14 (depends on 11)

A memory cell circuit according to claim 11, wherein said first inverter includes a first resistance disposed between said output terminal of said first inverter and a high-potential source and a second n-channel MOS transistor disposed between said output terminal and a low-potential source, and said second inverter includes a second resistance disposed between said output terminal of said second inverter and said high-potential source and a third n-channel MOS transistor disposed between said output terminal and said low-potential source.

### Claim 15 (depends on 14)

A memory cell circuit according to claim 14, wherein said high-potential source is a power source supplying a logic high potential, and said low-potential source is a power source supplying a logic low potential.