# US 5,353,246 A · Programmable semiconductor antifuse structure and method of fabricating

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- Number: US 5,353,246 A
- Document ID: US5353246A
- Status: Granted
- Kind: A
- Application number: 08/108,363
- Filed: 1993-08-18
- Granted: 1994-10-04
- Earliest claimed: 1991-10-18
- Assignees: Lattice Semiconductor Corporation
- Inventors: Wai M. Tsang; Daniel C. Hu; Dong T. Khong
- Web page: https://patentgrep.com/patent/US5353246A

## CPC

- H10W 20/065: {by making at least a portion of the conductive part non-conductive, e.g. by oxidation}
- H10D 48/381: {Multistable devices; Devices having two or more distinct operating states}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A programmable semiconductor antifuse structure and method of fabricating are provided which allow for miniaturization of components to an area of less than one micron. The cell exhibits a high pre-programmed resistance of more than 1.times.10.sup.7 ohms and has an extremely low programmed cell resistance of around 50 ohms.

## Claims

### Claim 1

The method of forming an electrical programmable read only memory cell having an antifuse structure comprising the steps of:
growing a first insulating layer on a silicon substrate;
depositing a first semiconductor layer on said first insulating layer;
doping said first semiconductor layer to a predetermined conductivity;
etching said first semiconductor layer;
depositing a second insulating layer over said first semiconductor layer and said first insulating layer;
etching said second insulating layer to form an opening which extends to and exposes a portion of said first semiconductor layer;
forming a conductive layer over said first semiconductor layer;
depositing a second semiconductor layer over said second insulating layer and said conductive layer;
etching said second semiconductor layer, wherein said second semiconductor layer overlies said conductive layer and a portion of said second insulating layer;
depositing a metal layer on said second semiconductor layer; and
etching said metal layer to form a contact to said memory cell.

### Claim 2 (depends on 1)

A method of claim 1 further comprising:
forming a passivation layer; and
removing a portion of said passivation layer on the periphery of said memory cell.

### Claim 3 (depends on 2)

The method of claim 2 further comprising:
performing an alloy to ensure all contacts are ohmic.

### Claim 4 (depends on 1)

The method of claim 1 wherein said step of forming said conductive layer comprises:
sputtering a layer of titanium;
performing a thermal annealing to form a layer of titanium silicide;
stripping unreacted titanium and titanium nitride; and
forming a layer of titanium nitride on said layer of titanium silicide.