# US 5,353,245 A · Memory integrated circuit with balanced resistance

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- Number: US 5,353,245 A
- Document ID: US5353245A
- Status: Granted
- Kind: A
- Application number: 08/111,033
- Filed: 1993-08-24
- Granted: 1994-10-04
- Earliest claimed: 1991-12-30
- Assignees: AT&T Bell Laboratories
- Inventors: Kuo-Hua Lee; Janmye Sung
- Web page: https://patentgrep.com/patent/US5353245A

## CPC

- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- Y10S 257/903: FET configuration adapted for use as static memory cell
- Y10S 257/904: with passive components,, e.g. polysilicon resistors
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

An integrated circuit, illustratively an SRAM, with pull down gates symmetrically positioned with respect to the ground line is disclosed. The symmetric positioning helps to insure cell stability.

## Claims

### Claim 1

A semiconductor integrated circuit comprising:
at least one memory cell, said cell comprising
a buried conductor;
first and second gates positioned on opposite sides of said conductor;
a first junction between said first gate and said buried conductor, said first gate controlling current flow from said first junction to said conductor;
a second junction between said second gate and said buried conductor, said second gate controlling current flow from said second junction to said conductor.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which said buried conductor is a ground line.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which said first and second gates are gates of SRAM pull down transistors.