# US 5,352,987 A · Analog multiplexer

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- Number: US 5,352,987 A
- Document ID: US5352987A
- Status: Granted
- Kind: A
- Application number: 08/095,285
- Filed: 1993-07-21
- Granted: 1994-10-04
- Earliest claimed: 1993-07-21
- Assignees: Elantec, Inc.
- Inventors: Barry Harvey
- Web page: https://patentgrep.com/patent/US5352987A

## CPC

- H03K 17/6264: {using current steering means}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An analog multiplier includes a plurality of input stages that are selectively coupled to inputs of a common amplifier through coupling elements and logic circuitry that selectively controls conduction through the coupling elements to the amplifier. The coupling elements include transistors that are common base connected to a bias supply for shunting capacitive feed through to the amplifier.

## Claims

### Claim 1

An analog multiplexer comprising:
an amplifier including a pair of inputs for forming an output from signals appearing on the pair of inputs thereof;
a plurality of input stages, each including a pair of transistors of one conductivity type having bases and collectors and having emitters commonly connected to receive bias signal;
logic means including emitter followers of the one conductivity type with emitters connected to the collectors of the transistors in each of the input stages for selectively shunting collector currents therethrough in response to applied logic signals; and
a coupling transistor of the one conductivity type stage, each coupling transistor having an emitter connected to the collector of each transistor in each of the input stages, and having a collector connected to one of the pair of inputs of the amplifier, and having a base connected to a source of bias signal for selectively conducting signal through the coupling transistors to the inputs of the amplifier in response to the associated logic means not conducting signal therethrough.