# US 5,352,945 A · Voltage compensating delay element

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- Number: US 5,352,945 A
- Document ID: US5352945A
- Status: Granted
- Kind: A
- Application number: 08/032,900
- Filed: 1993-03-18
- Granted: 1994-10-04
- Earliest claimed: 1993-03-18
- Assignees: Micron Semiconductor, Inc.
- Inventors: Stephen L. Casper; Daniel R. Loughmiller
- Web page: https://patentgrep.com/patent/US5352945A

## CPC

- H03K 5/133: using a chain of active delay devices
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A signal-delaying capacitive circuit applied to a node in a microcircuit device is immunized against the variation of the supply voltage by a metal-oxide semiconductor connected in series between the node and the signal-delaying capacitive circuit. The gate of the semiconductor is biased with a voltage signal proportional to the supply voltage, whereby the resistance of the semiconductor is increased as the supply voltage decreases; thus, isolating the capacitive circuit from the node and reducing the delay.

## Claims

### Claim 1

In an electronic circuit having a signal path comprising a series of inverters biased by a supply voltage in which a delaying capacitive element is connected in a shunt path at an intermediate node along said signal path at which said signal is being delayed, said shunt path containing said capacitive element between said intermediate node and a reference point, an improvement for compensating for variations in the delaying effect of said capacitive element as a result of variations in the circuit supply voltage, said improvement comprising:
a controllable resistance element connected in said shunt path in series with said capicitive element between said intermediate node and said reference point;
said resistance element having a resistivity controllable by said bias voltage wherein said resistivity increases and said delaying effect at said node increases when said bias voltage is increased; and
means for generating said bias voltage as a function of said supply voltage wherein said bias voltage is increased as the supply voltage increases.

### Claim 2 (depends on 1)

The improvement of claim 1, wherein said controllable resistance element comprises a transistor having a gate connected to said bias voltage supply.

### Claim 3 (depends on 2)

The improvement of claim 2, wherein said transistor is a first metal-oxide semiconductor.

### Claim 4 (depends on 3)

The improvement of claim 3, wherein said capacitive element comprises a second metal-oxide semiconductor having a source and a drain connected together.

### Claim 5 (depends on 4)

The improvement of claim 4, wherein said second semiconductor has a gate connected to said transistor, and said source and drain are connected together to said reference point.

### Claim 6 (depends on 5)

The improvement of claim 5, wherein said first metal-oxide semiconductor has a drain connected to said node, and a source connected to a gate of said second metal-oxide semiconductor.

### Claim 7 (depends on 4)

The improvement of claim 4, wherein said electronic circuit and said improvement are part of an integrated microcircuit device.

### Claim 8 (depends on 7)

The improvement of claim 7, wherein said electronic circuit is a ring oscillator.