# US 5,352,936 A · High voltage tolerant voltage pump constructed for a low voltage CMOS process > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,352,936 A - Document ID: US5352936A - Status: Granted - Kind: A - Application number: 08/073,160 - Filed: 1993-06-07 - Granted: 1994-10-04 - Earliest claimed: 1993-06-07 - Assignees: Intel Corporation - Inventors: Michael J. Allen - Web page: https://patentgrep.com/patent/US5352936A ## CPC - G05F 1/465: {Internal voltage generators for integrated circuits, e.g. step down generators} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract An integrated circuit charge pump which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. One of the devices has its body well connected to its drain terminal to provide a diode between the source and body well which allows the device to turn on and off when subject to a series of input pulses at its drain terminal. A third similarly biased N well P channel device is connected in series with the pair of P channel devices to provide the voltage pumping effect at an output terminal. These devices have been found capable of generating voltages levels of ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage. ## Claims ### Claim 1 An integrated circuit charge pump circuit manufactured in a P- substrate material comprising: a first P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to a first voltage source of a first level, the source terminal being connected to receive a second voltage of a second level higher than the first level; a second P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to the N well and the drain terminal of the second P channel N well field effect transistor device, the source terminal being connected to the drain terminal of the first P channel N well field effect transistor device; a third P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to the N well and the drain terminal of the third P channel N a well field effect transistor device, the source terminal being connected to the drain terminal of the second P channel N well field effect transistor device, the drain terminal being connected to an output circuit having an input capacitance; and a source of voltage pulses input at the drain of the second P channel N well field effect transistor device whereby the second voltage at the source terminal of the first P channel N well field effect transistor device is increased by a voltage essentially equal to the voltage pulses and furnished to the output circuit by the third P channel N well field effect transistor. ### Claim 2 (depends on 1) An integrated circuit charge pump circuit as claimed in claim 1 in which the voltage pulses input at the drain of the second P channel N well field effect transistor device are of the first level. ### Claim 3 An integrated circuit comprising: a plurality of circuit devices joined in a circuit and designed to function with source voltages having a first value; and a charge pump circuit designed to function with source voltages of a second higher level, the charge pump circuit being manufactured in a P- substitute material and comprising a first P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to a first voltage source of a first level, the source terminal being connected to receive a second voltage of a second level higher than the first level; a second P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to the N well and the drain terminal of the second P channel N well field effect transistor device, the source terminal being connected to the drain terminal of the first P channel N well field effect transistor device; a third P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to the N well and the drain terminal of the third P channel well field effect transistor device, the source terminal being connected to the drain terminal of the second P channel N well field effect transistor device, the drain terminal being connected to an output circuit having an input capacitance; and a source of voltage pulses input at the drain of the second P channel N well field effect transistor device whereby the second voltage at the source terminal of the first P channel N well field effect transistor device is increased by a voltage essentially equal to the voltage pulses and furnished to the output circuit by the third P channel N well field effect transistor. ### Claim 4 (depends on 3) An integrated circuit as claimed in claim 3 in which the voltage pulses input at the drain terminal of the second P channel N well field effect transistor device are of the first level. ### Claim 5 An integrated circuit charge pump circuit comprising first, second, third, and fourth circuit nodes; first means for transferring any voltage of a first level from the first node to the second node; first diode means for providing a voltage at the second node to the third node whenever a voltage level at the second node is greater than a voltage level at the third node; means for storing a charge at the third node, second diode means for providing a voltage at the third node to the fourth node whenever a voltage level at the third node is greater than a voltage level at the fourth node; means for storing a charge at the fourth node, and means for alternately raising and lowering a level of voltage at the third node to alternately bias the first diode means to cease transferring current when a voltage level is raised and to transfer current when a voltage level is lowered and simultaneously to alteratively bias the second diode means to transfer current when a voltage level is raised and to cease transferring current when a voltage level is low. ### Claim 6 (depends on 5) An integrated circuit charge pump circuit as claimed in claim 5 in which the first and second diodes are formed in a current comprising a P channel N well field effect transistor having source, gate, and drain terminals, the gate terminal being connected to the N well and the drain terminal of the P channel N well field effect transistor device. ### Claim 7 (depends on 6) An integrated circuit charge pump circuit as claimed in claim 6 in which the first means for transferring any voltage of a first level from the first node to the second node comprises a P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to a voltage source less than the first level, the source terminal being connected to the first node, and the drain terminal being connected to the second node. ### Claim 8 (depends on 7) An integrated circuit charge pump circuit as claimed in claim 7 in which the means for storing a charge at the third node comprises a capacitor having first and second terminals, the first terminal being connected to the third node; and in which the means for alternately raising and lowering a level of voltage at the third node comprises means for furnishing a series of voltage pulses at the second terminal of the capacitor. ### Claim 9 (depends on 5) An integrated circuit charge pump circuit as claimed in claim 5 in which the first means for transferring any voltage of a first level from the first node to the second node comprises first P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to a voltage source less than the first level, the source terminal being connected to the first node, and the drain terminal being connected to the second node. ### Claim 10 (depends on 9) An integrated circuit charge pump circuit as claimed in claim 9 in which the means for storing a charge at the third node comprises a capacitor having first and second terminals, the first terminal being connected to the third node; and in which the means for alternately raising and lowering a level of voltage at the third node comprises means for furnishing a series of voltage pulses at the second terminal of the capacitor. ### Claim 11 (depends on 10) An integrated circuit charge pump circuit as claimed in claim 10 in which the first and second diodes are formed in a circuit comprising: a P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to the N well and the drain terminal of the P channel N well field effect transistor device. ### Claim 12 An integrated circuit comprising: a plurality of circuit joined in a circuit and designed to function with source voltage having a first value; and a charge pump circuit designed to function with source voltages of a second higher level, the circuit charge pump circuit comprising first, second, third and fourth circuit nodes; first means for transferring any voltage of second level from the first node to the second node; first diode means for providing a voltage at the second node to the third node whenever a voltage level at the second node is greater than the voltage level at the third node; means for storing a charge at the third node, second diode means for providing a voltage at the third node to the fourth node whenever a voltage level at the third node is greater than a voltage level at the fourth node; means for storing a charge at the fourth node; and means for alternately raising and lowering a level of voltage at the third node to alternately bias the first diode means to cease transferring current when a voltage level is raised and to transfer current when a voltage level is lowered and simultaneously to alternatively bias the second diode means to transfer current when a voltage level is raised and to cease transferring current when a voltage level is low. ### Claim 13 (depends on 12) An integrated circuit as claimed in claim 12 in which the first and second diodes are formed in a current comprising a P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to the N well and the drain terminal of the P channel N well field effect transistor device. ### Claim 14 (depends on 13) An integrated circuit as claimed in claim 13 in which the first means for transferring any voltage of a second level from the first node to the second node comprises a P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to a voltage source of the first level, the source terminal being connected to the first node, and the drain terminal being connected to the second node. ### Claim 15 (depends on 14) An integrated circuit as claimed in claim 14 in which the means for storing a charge at the third node comprises a capacitor having first and second terminals, the first terminal being connected to the third node; and in which the means for alternately raising and lowering a level of voltage at the third node comprises means for furnishing a series of voltage pulses of the first level at the second terminal of the capacitor. ### Claim 16 (depends on 12) An integrated circuit as claimed in claim 12 in which the first means for transferring any voltage of a second level from the first node to the second node comprises first P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to a voltage source of the first level, the source terminal being connected to the first node, and the drain terminal being connected to the second node. ### Claim 17 (depends on 16) An integrated circuit as claimed in claim 16 in which the means for storing a charge at the third node comprises a capacitor having first and second terminals, the first terminal being connected to the third note; and in which the means for alternately raising and lowering a level of voltage at the third node comprises means for furnishing a series of voltage pulses of the first level at the second terminal of the capacitor. ### Claim 18 (depends on 17) An integrated circuit as claimed in claim 17 in which the first and second diodes are formed in a circuit comprising a P channel N well field effect transistor device having source, gate, and drain terminals, the gate terminal being connected to the N well and the drain terminal of the P channel N well field effect transistor device.