# US 5,352,927 A · Self-aligned contact studs for semiconductor structures

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- Number: US 5,352,927 A
- Document ID: US5352927A
- Status: Granted
- Kind: A
- Application number: 07/968,634
- Filed: 1992-10-29
- Granted: 1994-10-04
- Earliest claimed: 1991-10-29
- Assignees: International Business Machines Corporation
- Inventors: Donna R. Cote; David Stanasolovich; Ronald A. Warren
- Web page: https://patentgrep.com/patent/US5352927A

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer for forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a diffusion region formed in said substrate;
a gate conductor formed over said substrate adjacent to said diffusion region, said gate conductor having a sidewall;
an insulating cap formed on said gate conductor;
an insulating alignment structure formed on said substrate, and aligned with and contacting said sidewall of said gate conductor, said insulating alignment structure having a sidewall, and said insulating alignment structure comprising material which etches at a faster rate than said insulating cap; and
an electrically conducting stud electrically contacting said diffusion region, and being aligned with said sidewall of said insulating alignment structure such that said insulating alignment structure prevents electrical contact between said electrically conducting stud and said gate conductor, and said electrically conducting stud having an exposed top surface which is coplanar with said insulating cap and coplanar with said insulating alignment structure for providing an electrical contact point for allowing electrical connection to said diffusion region.

### Claim 2

A semiconductor device, comprising:
a substrate;
a diffusion region formed in said substrate;
a gate conductor formed over said substrate adjacent to said diffusion region, said gate conductor having a sidewall;
an insulating cap formed on said gate conductor;
an insulating alignment structure formed on said substrate, and aligned with and contacting said sidewall of said gate conductor, said insulating alignment structure having a sidewall, and said insulating alignment structure comprising material which etches at a faster rate than said insulating cap;
an electrically conducting stud electrically contacting said diffusion region, and being aligned with said sidewall of said insulating alignment structure such that said insulating alignment structure prevents electrical contact between said electrically conducting stud and said gate conductor, and said electrically conducting stud having an exposed top surface which is coplanar with said insulating cap and coplanar with said insulating alignment structure for providing an electrical contact point for allowing electrical connection to said diffusion region; and
insulating means for insulating said gate conductor and said electrically conducting stud, whereby the exposed top surface of said electrically conducting stud is not insulated by said insulating means, and wherein said insulating means polishes at a faster rate than boron nitride, and said insulating means etches at a slower rate than boron nitride, and wherein said electrically conducting stud has boundaries defined by said insulating alignment structure and said insulating means.

### Claim 3

A semiconductor device, comprising:
a substrate;
a diffusion region formed in said substrate;
a gate conductor formed over said substrate adjacent to said diffusion region, said gate conductor having a sidewall;
an insulating cap comprising oxide and being formed on said gate conductor;
an insulating alignment structure comprising nitride and being formed on said substrate, and aligned with and contacting said sidewall of said gate conductor, said insulating alignment structure having a sidewall, and said insulating alignment structure comprising material which etches at a faster rate than said insulating cap; and
an electrically conducting stud electrically contacting said diffusion region, and being aligned with said sidewall of said insulating alignment structure such that said insulating alignment structure prevents electrical contact between said electrically conducting stud and said gate conductor, and said electrically conducting stud having an exposed top surface which is coplanar with said insulating cap and coplanar with said insulating alignment structure for providing an electrical contact point for allowing electrical connection to said diffusion region.