# US 5,352,924 A · Bipolar layout for improved performance

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- Number: US 5,352,924 A
- Document ID: US5352924A
- Status: Granted
- Kind: A
- Application number: 08/048,531
- Filed: 1993-04-14
- Granted: 1994-10-04
- Earliest claimed: 1993-04-14
- Assignees: Texas Instruments Incorporated
- Inventors: Shivaling Mahant-Shetti; David B. Scott
- Web page: https://patentgrep.com/patent/US5352924A

## CPC

- H10D 10/421: {having both emitter-base and base-collector junctions ending at the same surface of the body}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A bipolar transistor is disclosed which substantially reduces prior art problems associated with current crowding by maximizing the active periphery of the transistor's emitter [10].

## Claims

### Claim 1

A plurality of integrated circuit devices being arranged in a hexagonal close packed formation in a plane, wherein each said device is of circular symmetry and comprises:
a base;
a collector;
a cylindrically shaped emitter, which during device operation, said base, emitter and collector operate collectively as a transistor; and
a plurality of base contacts spaced apart from said emitter at substantially equal radii from the center of mass of said cylindrically shaped emitter.

### Claim 2 (depends on 1)

A plurality of integrated circuit devices as recited in claim 1 wherein selected emitters of said devices are connected together with poly and wherein selected bases of said devices are connected together.

### Claim 3 (depends on 1)

A plurality of integrated circuit devices as retired in claim 1 wherein poly connects selected emitters of said devices, said poly being routed so as to maximize the active portion of said devices.