# US 5,352,629 A · Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,352,629 A - Document ID: US5352629A - Status: Granted - Kind: A - Application number: 08/006,297 - Filed: 1993-01-19 - Granted: 1994-10-04 - Earliest claimed: 1993-01-19 - Assignees: General Electric Company - Inventors: Kyung W. Paik; William A. Hennessy; Wolfgang Daum - Web page: https://patentgrep.com/patent/US5352629A ## CPC - H10W 70/68: Shapes or dispositions thereof - H10W 70/682: {comprising holes having chips therein} - H10W 72/0711: {Apparatus therefor} - H10W 72/07125: {Means for controlling the bonding environment, e.g. valves or vacuum pumps} - H10W 72/07141: {Means for applying energy, e.g. ovens or lasers} - H10W 72/073: {of die-attach connectors} - H10W 72/07331: {Connecting techniques} - H10W 72/07333: {Ultrasonic bonding, e.g. thermosonic bonding} - H10W 72/07336: {Soldering or alloying} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for attaching a chip to a substrate includes providing the substrate with an outer layer of an electrical conductor which is not wettable by solder and which has a window exposing an inner layer of electrical conductor that is wettable by solder. A solder preform is placed on the window exposing the inner layer, and the chip is placed on the solder preform. The substrate is then heated so as to melt the solder preform. To achieve planarity, the substrate is be positioned in a pressurizing chamber with a film overlay having higher pressure above the film overlay than underneath the overlay, and heated above the melting point of the solder. ## Claims ### Claim 1 A method for attaching at least one semiconductor chip, with an electrical conductor disposed on an underside of each of said at least one chip, to a substrate having a surface, to cause self-alignment and PLANARIZATION of said at least one chip, comprising: providing on said substrate surface an inner layer of electrical conductor having solder wettability; providing on said inner layer an outer layer of electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip; placing a solder preform on each respective one of said at least one window; placing a chip on each respective one of said solder preforms; placing said substrate into a structure capable of applying isostatic pressure; overlaying said substrate and said at least one chip with a dielectric film layer; applying pressure over said dielectric film layer; and subsequently heating said substrate above the melting point of said solder preforms to align each of said at least one chip within said at least one window, and substantially simultaneously to planarize said at least one chip with respect to said surface. ### Claim 2 (depends on 1) The method of claim 1, further including the step of providing chip wells in said substrate prior to providing said substrate with said outer layer and said inner layer. ### Claim 3 (depends on 2) The method of claim 2, wherein the step of providing chip wells comprises providing chip wells with slanted sidewalls. ### Claim 4 (depends on 2) The method of claim 2, further including the step of applying a vacuum under said dielectric film layer during the step of applying pressure over said dielectric film layer. ### Claim 5 (depends on 4) The method of claim 4, wherein said dielectric film layer comprises a polyimide. ### Claim 6 (depends on 4) The method of claim 4, further including the step of cooling said substrate while still applying said vacuum after the step of heating said substrate. ### Claim 7 (depends on 4) The method of claim 4, further including the steps of cooling said substrate after the step of heating said substrate, and thereafter removing said dielectric layer. ### Claim 8 A method for attaching at least one semiconductor chip, each with an electrical conductor disposed on an underside thereof, to a substrate having a surface, and having chip wells therein, causing chip attachment, chip alignment, and chip planarization substantially simultaneously, comprising: providing on said substrate surface an inner layer of electrical conductor having solder wettability; providing on said inner layer an outer layer of an electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip; placing a solder preform on each respective one of said at least one window; placing a chip on each respective one of said solder preforms; placing said substrate into a structure capable of applying isostatic pressure; overlaying said substrate and said at least one chip with a dielectric film layer; applying pressure over said dielectric film layer; and subsequently heating said substrate above the melting point of said solder preforms to cause each of said at least one chip to be substantially simultaneously self-aligned within said at least one window and planarized with respect to said surface. ### Claim 9 (depends on 8) The method of claim 8, wherein the step of providing said outer layer having windows exposing said inner layer is performed so that each respective window has a length and width substantially equal to the length and width of a predetermined respective one of said chips; and the step of placing a solder preform on each respective one of said windows is performed so that each respective solder preform has a length and width substantially equal to the length and width of the respective window on which it is situated. ### Claim 10 (depends on 9) The method of claim 9, further including the step of applying a vacuum under said dielectric film layer during the step of applying pressure over said dielectric film layer. ### Claim 11 (depends on 10) The method of claim 10, wherein said chip wells have slanted sidewalls. ### Claim 12 (depends on 8) The method of claim 8, further including the steps of: applying a first solder flux on said inner layer through said windows prior to placing said preforms in said windows; and applying a second solder flux on said solder preforms prior to placing said chips on said solder preforms.