# US 5,352,621 A · Method for manufacturing an internally shielded dynamic random access memory cell

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- Number: US 5,352,621 A
- Document ID: US5352621A
- Status: Granted
- Kind: A
- Application number: 08/046,201
- Filed: 1993-04-14
- Granted: 1994-10-04
- Earliest claimed: 1992-04-17
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Jae-Kap Kim; In-Sool Chung
- Web page: https://patentgrep.com/patent/US5352621A

## CPC

- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/05: {Making the transistor}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In the manufacturing process of a Dynamic Random Access Memory cell, the conducting layer used for preventing the capacitive coupling between a bit line and a word line is formed over the surface of the entire memory cell excepting the contact legion of a bit line and a storage electrode. Moreover, as the conducting layer used for preventing the capacitive coupling is used as an etching barrier in the etching process forming a contact hole, self-aligned contacts are formed. Therefore, the operation of the unwanted cell of a Dynamic Random Access Memory cell caused by the capacitive coupling is protected and a highly integrated Dynamic Random Access Memory cell is manufactured.

## Claims

### Claim 1

A method for manufacturing an internally shielded Dynamic Random Access Memory cell comprising the steps of:
forming vertically a word line conductively isolated from a silicon substrate;
forming a first insulating layer on said word line;
forming an electrically conducting layer used for preventing the capacitive coupling of said word line and a bit line on said first insulating layer, said conducting layer being conductively isolated from said word line;
forming a second insulating layer used for forming an even surface on said conducting layer;
forming horizontally said bit line conductively isolated from said conducting layer and electrically coupled to a section of said silicon substrate the conductivity of which depends upon a voltage applied to said word line; and
forming a storage electrode electrically coupled to said section of said silicon substrate, said storage electrode being conductively isolated from said conducting layer.

### Claim 2 (depends on 1)

A method for manufacturing a Dynamic Random Access Memory cell claimed in claim 1, wherein said bit line is vertically formed in an active region and between said active regions.

### Claim 3 (depends on 2)

A method for manufacturing a Dynamic Random Access Memory cell claimed in claim 2, wherein said conducting layer is formed by a silicon layer or a metal layer.

### Claim 4

A method for manufacturing an internally shielded Dynamic Random Access Memory cell comprising the steps of:
forming a field oxide layer in the non-active region of a silicon substrate;
forming a MOSFET having a gate oxide layer, a word line and a source/drain;
forming a first insulating layer over the entire surface;
forming an electrically conducting layer used for preventing the capacitive coupling of said word line and a bit line and a second insulating layer used for forming an even surface on said first insulating layer, said conducting layer being conductively isolated from said word line;
forming a contact hole by etching said second insulating layer, said conducting layer and said first insulating layer in the region of a bit line contact until said source of said MOSFET is exposed;
forming an insulating spacer on the sidewall of said exposed conducting layer;
forming said bit line electrically coupled to said source, said bit line being conductively isolated from said conducting layer;
forming a third insulating layer used for forming an even surface over the entire surface;
forming a contact hole by etching said third insulating layer, said second insulating layer, said conducting layer and said first insulating layer in the contact region of a storage electrode until said drain is exposed;
forming an insulating spacer on the sidewall of said exposed conducting layer; and
forming a storage electrode electrically coupled to said drain, said storage electrode being conductively isolated from said conducting layer.

### Claim 5 (depends on 4)

A method for manufacturing a Dynamic Random Access Memory cell claimed in claim 4, wherein said conducting layer used for preventing the capacitive coupling of said word line and said bit line is formed by a silicon layer or a metal layer.

### Claim 6 (depends on 5)

A method for manufacturing a Dynamic Random Access Memory cell claimed in claim 5, wherein said second insulating layer and said third insulating layer are made of Boro-Phospho-silicate-glass or undoped-silicate-glass.