# US 5,352,617 A · Method for manufacturing Bi-CMOS transistor devices

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- Number: US 5,352,617 A
- Document ID: US5352617A
- Status: Granted
- Kind: A
- Application number: 08/051,520
- Filed: 1993-04-26
- Granted: 1994-10-04
- Earliest claimed: 1992-04-27
- Assignees: Sony Corporation
- Inventors: Hiroyuki Miwa
- Web page: https://patentgrep.com/patent/US5352617A

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor is disclosed, which comprises covering the bipolar transistor formation region with a gate insulating film and also with a first gate formation material at the time of the MOS transistor gate formation, removing the first gate formation material and gate insulating film covering at least a portion of the bipolar transistor formation region, thus forming an opening in the gate insulating film and first gate formation material, forming a second gate formation material, removing other portion of the first and second gate formation materials than on the bipolar transistor formation region and the MOS transistor gate formation region, forming an inter-layer insulating film, and removing the inter-layer insulating film and first and second gate formation materials on at least a portion of the bipolar transistor formation region, thus forming a second opening in the first-mentioned opening in the inter-layer insulating film and first and second gate formation materials.

## Claims

### Claim 1

A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor comprising the steps of:
covering the bipolar transistor formation region with a gate insulating film and also with a first gate formation material at the time of the MOS transistor gate formation;
removing the first gate formation material and gate insulating film covering at least a portion of said bipolar transistor formation region, thus forming an opening in said gate insulating film and first gate formation material;
forming a second gate formation material;
removing other portions of said first and second gate formation materials on said bipolar transistor formation region and the MOS transistor gate formation region;
forming an inter-layer insulating film; and
removing the inter-layer insulating film and first and second gate formation materials on at least a portion of the bipolar transistor formation region, thus forming a second opening in said first-mentioned opening in said inter-layer insulating film and first and second gate formation materials.

### Claim 2

A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor comprising the steps of:
covering the bipolar transistor formation region with a gate insulating film and also with a first gate formation material at the time of the MOS transistor gate formation;
removing the first gate formation material and gate insulating film covering at least a portion of said bipolar transistor formation region, thus forming an opening in said gate insulating film and first gate formation material;
forming a second gate formation material;
removing other portions of said first and second gate formation materials on said bipolar transistor formation region and the MOS transistor gate formation region;
forming an inter-layer insulating film;
removing the inter-layer insulating film and first and second gate formation materials on at least a portion of the bipolar transistor formation region, thus forming a second opening in said first-mentioned opening in said inter-layer insulating film and first and second gate formation materials;
forming an insulating film side wall within said first-mentioned opening; and
burying a conductor in said first-mentioned opening.

### Claim 3 (depends on 1, 2)

The method of manufacturing a semiconductor device according to claims 1 or 2, wherein said first gate formation material is polysilicon.

### Claim 4 (depends on 1, 2)

The method of manufacturing a semiconductor device according to claims 1 or 2, wherein said conductor buried in said opening is polysilicon.

### Claim 5

A method of manufacturing a semiconductor comprising the steps of:
forming a buried layer;
forming an epitaxial layer;
etching said epitaxial layer such as to leave a portion thereof on a portion of an emitter/base formation region of a bipolar transistor;
forming a first conductor; and
removing a portion of said first conductor on a base electrode region of said bipolar transistor; and
removing the first conductor on said emitter/base formation region and also simultaneously removing the epitaxial layer on a collector electrode region of said bipolar transistor.

### Claim 6

A method of manufacturing a semiconductor comprising the steps of:
forming a buried layer;
forming an epitaxial layer;
etching said epitaxial layer such as to leave a portion thereof on a portion of an emitter/base formation region of a bipolar transistor;
forming a first conductor;
removing a portion of said first conductor on a base electrode region of said bipolar transistor;
removing the first conductor on said emitter/base formation region and also simultaneously removing the epitaxial layer on a collector electrode region of said bipolar transistor;
forming a second conductor; and
forming high impurity concentration diffusion regions for emitter and collector electrode simultaneously with said second conductor as a source of diffusion.

### Claim 7 (depends on 5)

The method of manufacturing a semiconductor device according to claim 5, wherein said first and second conductors are polycrystalline silicon or a lamination of polycrystalline silicon and a high-melting metal.

### Claim 8 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein said first and second conductors are polycrystalline silicon or a lamination between polycrystalline silicon and a high-melting metal.