# US 5,351,301 A · Authenticator circuit

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- Number: US 5,351,301 A
- Document ID: US5351301A
- Status: Granted
- Kind: A
- Application number: 06/129,047
- Filed: 1980-03-03
- Granted: 1994-09-27
- Earliest claimed: 1980-03-03
- Assignees: The United States of America as represented by the Director, National Security Agency
- Inventors: Ronald M. Benincasa
- Web page: https://patentgrep.com/patent/US5351301A

## CPC

- G06F 7/584: {using finite field arithmetic, e.g. using a linear feedback shift register}
- H04L 9/0662: {with particular pseudorandom sequence generator}
- H04L 9/32: including means for verifying the identity or authority of a user of the system {or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials}
- G06F 2207/581: Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
- G06F 2207/583: Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs
- H04L 2209/12: Details relating to cryptographic hardware or logic circuitry
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An authenticator circuit and message authentication apparatus. The circuit includes a plurality of shift register stages, some of which are separated by adders having an input from a succeeding stage. Switching circuits selectively control the second adder inputs to determine the shifting sequence of information passing through the register stages. A message authentication apparatus includes a key generator and authenticator circuit converted at the output of a transmitter. The input of a receiver includes a similar authenticator circuit and key generator, plus a counter.

## Claims

### Claim 1

An apparatus, comprising:
a plurality of delay stages connected to form a shift register;
a first mod-2 adder inserted between two consecutive stages of said register, the output of the preceeding stage forming one input of said adder and the output of the adder forming the input to the succeeding stage;
a first terminal for providing information to said apparatus;
a second terminal for providing information to said apparatus;
a second mod-2 adder having an input from said first terminal, an input from the last stage of said register, and an output connected to the first stage of said register;
means controlled by data provided on said second terminal for selectively switching either the information in the last delay stage or a zero to the second input of said first adder; and
an output terminal connected to a selected one of said register stages.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
a plurality of mod-2 adders each inserted between two consecutive stages of said register in the manner of said first adder, and
wherein said control means includes means for selectively switching either the information in the last delay stage or a zero to the second input of each of said plurality of adders.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein said control means includes a two-input binary AND gate having a first input from said last stage, a second input from said second terminal, and an output connected to the second input of said first adder.

### Claim 4 (depends on 1, 2)

The apparatus of claim 1 or 2, further comprising:
a key generator connected to said second terminal;
a communications path including a data input; and
means for selectively switching either said data input or said output terminal to said first terminal.

### Claim 5 (depends on 1, 2)

The apparatus of claim 1 or 2, further comprising:
a key generator connected to said second terminal;
a communications path including a data input connected to said first terminal; and
means for comparing signals provided on said data input and said output terminal.

### Claim 6 (depends on 5)

The apparatus of claim 5 wherein said comparing means includes means for counting the number of consecutive signal data agreements.

### Claim 7 (depends on 5)

The apparatus of claim 5 wherein said comparing means includes:
a counter, and
a mod-2 adder operatively connected to sum the signals on the output of said data input and said output terminal and to provide the result as the input of said counter.