# US 5,351,206 A · Signed two's complement constant multiplier compiler

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- Number: US 5,351,206 A
- Document ID: US5351206A
- Status: Granted
- Kind: A
- Application number: 07/976,233
- Filed: 1992-11-12
- Granted: 1994-09-27
- Earliest claimed: 1992-11-12
- Assignees: VLSI Technology, Inc.
- Inventors: Lin Yang; Chun-Ling Liu
- Web page: https://patentgrep.com/patent/US5351206A

## CPC

- G06F 30/30: Circuit design
- G06F 7/523: Multiplying only
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A constant multiplier compiler model allows a signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a signed two's complement constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant is automatically generated by modifying a netlist of a precursor signed two's complement constant multiplier circuit for computing a product of the multi-bit multiplicand and a multi-bit constant that is all ones. For each zero in the multi-bit constant, a corresponding logical column of full adders is deleted and each output signal of each adder so deleted is logically connected to a corresponding output signal in a preceding logical column of adders. Two exceptions to the foregoing rule occur. In the case of a first logical column of adders having no preceding logical column of adders, each output signal of each adder deleted is logically connected to a bit of the multi-bit multiplicand. In the case of a logical row of adders receiving a most significant bit of the multi-bit multiplicand, each output signal of each adder deleted is logically connected to one of the most significant bit of the multi-bit multiplicand and logic zero. The method produces a minimum layout, minimizing silicon cost, and produces a high performance design with critical paths optimized in terms of time delay.

## Claims

### Claim 1

A signed two's complement constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant that uses full adders each having three input terminals and two output terminals, a Sum output terminal and a Carry output terminal, certain ones of said input terminals and said output terminals being weighted so as to represent positive and negative numbers, the circuit comprising:
an interconnected array of full adders logically arranged in rows and columns, full adders in an input column each receiving different ones of said bits of said multi-bit multiplicand, full adders in each of two output columns each producing a product bit, each column besides said output columns producing a partial product, with each full adder in each row in columns besides said output columns receiving a same one of said bits of said multi-bit multiplicand;
wherein, for multi-bit constants that are neither all ones nor all zeros, a number of columns is less than said number of bits of said multiplicand, said array of full adders being interconnected such that partial products corresponding to zeros in said constant are not produced.