# US 5,351,145 A · Active matrix substrate device and related method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,351,145 A - Document ID: US5351145A - Status: Granted - Kind: A - Application number: 07/818,573 - Filed: 1992-01-09 - Granted: 1994-09-27 - Earliest claimed: 1991-01-14 - Assignees: Matsushita Electric Industrial Co., Ltd. - Inventors: Yutaka Miyata; Mamoru Furuta; Tatsuo Yoshioka; Hiroshi Tsutsu; Tetsuya Kawamura - Web page: https://patentgrep.com/patent/US5351145A ## CPC - G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 3/3659: {the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes} - G09G 3/3677: {suitable for active matrices only} - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - G02F 1/136245: {having complementary transistors} - G09G 2300/0823: used to establish symmetry in driving, e.g. with polarity inversion - G09G 2320/0204: Compensation of DC component across the pixels in flat panels - G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling - G11C: STATIC STORES (semiconductor memory devices H10B) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract An active matrix substrate includes a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to the n-type and p-type transistors for controlling the n-type and p-type transistors, and pixel-corresponding electrodes controlled by the transistor pairs respectively. Drains of an n-type transistor and a p-type transistor in each of the pairs are connected to each other via a related pixel corresponding electrode. First pulses are applied to gates of the n-type transistors. Second pulses are applied to gates of the p-type transistors. There is provided a difference in phase between the first pulses and the second pulses. ## Claims ### Claim 1 A method of driving an active matrix substrate comprising a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to said n-type and p-type transistors for controlling said n-type and p-type transistors, and pixel-corresponding electrodes controlled by said transistor pairs respectively, wherein drains of an n-type transistor and a p-type transistor in each of said pairs are connected to each other via a related pixel corresponding electrode, the method comprising the steps of: applying first pulses to gates of said n-type transistors in one field interval; applying second pulses to gates of said p-type transistors in said one field interval; and providing a difference in phase between said first pulses and said second pulses. ### Claim 2 A method of driving an active matrix substrate comprising a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to said n-type and p-type transistors for controlling said n-type and p-type transistors, and pixel-corresponding electrodes controlled by said transistor pairs respectively, wherein drains of an n-type transistor pairs respectively, wherein drains of an n-type transistor and a p-type transistor in each of said pairs are connected to each other via a related pixel corresponding electrode, the method comprising the steps of: applying first pulses to gates of said n-type transistors; applying second pulses to gates of said p-type transistors; and providing a different in pulse width between said first pulses and said second pulses; wherein a first pulse and a second pulse are respectively applied to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during a selection of said pixel-corresponding electrode. ### Claim 3 (depends on 2) The method of claim 2, further comprising the steps of changing a pulse width of said first pulses every field, and changing a pulse width of said second pulses every field. ### Claim 4 (depends on 2) The method of claim 2, further comprising the steps of changing a pulse width of said first pulses every frame, and changing a pulse width of said second pulses every frame. ### Claim 5 A method of driving an active matrix substrate comprising a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to said n-type and p-type transistors for controlling said n-type and p-type transistors, and pixel-corresponding electrodes controlled by said transistor pairs respectively, wherein drains of an n-type transistor and a p-type transistor in each of said pairs are connected to each other via a related pixel corresponding electrode, the method comprising the steps of: scanning said pixel-corresponding electrodes; and applying a gate pulse to a gate of one of an n-type transistor and a p-type transistor in each of said pairs before a horizontal scanning period for which a related pixel-corresponding electrode is scanned. ### Claim 6 A method of driving an active matrix substrate comprising a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to said n-type and p-type transistors for controlling said n-type and p-type transistors, and pixel-corresponding electrodes controlled by said transistor pairs respectively, wherein drains of an n-type transistor and a p-type transistor in each of said pairs are connected to each other via a related pixel corresponding electrode, the method comprising the steps of: applying first pulses to gates of said n-type transistors; applying second pulses to gates of said p-type transistors; and providing a difference in pulse height between said first pulses and said second pulses; wherein a first pulse and a second pulse are respectively applied to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during a selection of said pixel-corresponding electrode. ### Claim 7 An apparatus comprising: an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair; first feeding means for feeding a first pulse to gates of n-type switching transistors in said pairs contained in a common row of the matrix in one field interval; second feeding means for feeding a second pulse to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said one field interval; and phase difference means for providing a difference in phase between the first pulse and the second pulse. ### Claim 8 An apparatus comprising: an active matrix substrate having pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel-corresponding electrode via the pair; first means for feeding a first pulse to gates of n-type switching transistors in said pairs contained in a common row of the matrix in a given interval; second means for feeding a second pulse to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval; and means for providing a difference in pulse width between the first pulse and the second pulse; wherein said first and second means include means for respectively applying a first pulse and a second pulse to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during a selection of said pixel-corresponding electrode. ### Claim 9 An apparatus comprising: an active matrix substrate having pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel-corresponding electrode via the pair; first means for feeding a first pulse to gates of n-type switching transistors in said pairs contained in a common row of the matrix in a given interval; second means for feeding a second pulse to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval; and means for providing a different in pulse height between the first pulse and the second pulse; wherein said first and second means include means for respectively applying a first pulse and a second pulse to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during a selection of said pixel-corresponding electrode. ### Claim 10 An apparatus comprising: an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair; first feeding means for feeding a first pulse to gates of n-type switching transistors in said pairs contained in a common row of the matrix in a given interval; second feeding means for feeding a second pulse to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval; and phase difference means for providing a difference in phase between the first pulse and the second pulse, wherein said first and second means include means for respectively applying both a first pulse and a second pulse to respective gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during access to said pixel-corresponding electrode. ### Claim 11 A method of driving an active matrix substrate comprising a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to said n-type and p-type transistors for controlling said n-type and p-type transistors, and pixel-corresponding electrodes controlled by said transistor pairs respectively, wherein drains of an n-type transistor and a p-type transistor in each of said pairs are connected to each other via a related pixel corresponding electrode, the method comprising the steps of: applying first pulses to gates of said n-type transistors; applying second pulses to gates of said p-type transistors; and providing a difference in phase between said first pulses and said second pulses, wherein said steps of applying said first and second pulses comprises respectively applying both a first pulse and a second pulse to gates of an n-type transistor and a p-type transistor in a pair related to a pixel-corresponding electrode during access to said pixel-corresponding electrode. ### Claim 12 An apparatus comprising: an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair; first means for applying a first sequence of pulses to gates of n-type switching transistors of said pairs contained in a common row of the matrix in one field interval; second means for applying a second sequence of pulses to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said one field interval; and timing means for providing a timing difference between the first and second sequences of pulses for reducing DC offset in pixel-corresponding electrodes connected to said pairs contained in said common row of the matrix. ### Claim 13 An apparatus comprising: an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistor, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair; first means for applying a first sequence of pulses to gates of n-type switching transistors of said pairs contained in a common row of the matrix in a given interval; second means for applying a second sequence of pulses to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval; and timing means for providing a timing difference between the first and second sequences of pulses for reducing DC offset in pixel-corresponding electrodes connected to said pairs contained in said common row of the matrix, wherein said timing means comprises phase means for applying both said first and sequences of pulses to both said n-type and p-type transistors of a pair when a related pixel-corresponding electrode is being accessed and for causing alternate ones of said first sequence of pulses to precede corresponding ones of said second sequence of pulses applied to said pairs contained in said common row of the matrix, and for causing remaining ones of said first sequence of pulses to follow corresponding ones of said second sequence of pulses applied to said pairs contained in said common row of the matrix. ### Claim 14 (depends on 13) The apparatus recited in claim 13, wherein said phase means comprises delay means connected to said first and second means for providing delayed pulses respectively corresponding to and delayed from said first and second sequences of pulses, and switching means for selecting between said first and second sequences of pulses and said delayed pulses for application to corresponding n-type and p-type switching transistors of said pairs contained in said common row of the matrix. ### Claim 15 An apparatus comprising: an active matrix substrate including pairs each having an n-type switching transistor and a p-type switching transistors, and pixel-corresponding electrodes connected to said pairs respectively, wherein said pairs are arranged in a matrix, wherein each of said pixel-corresponding electrodes is connected to ends of source-drain paths of an n-type switching transistor and a p-type switching transistor in a related pair, and wherein when at least one of an n-type switching transistor and a p-type switching transistor in each of said pair is made conductive, an information signal can be transmitted to a related pixel- corresponding electrode via the pair; first means for applying a first sequence of pulses to gates of n-type switching transistors of said pairs contained in a common row of the matrix in a given interval; second means for applying a second sequence of pulses to gates of p-type switching transistors in said pairs contained in said common row of the matrix in said given interval; and timing means for providing a timing difference between the first and second sequences of pulses for reducing DC offset in pixel-corresponding electrodes connected to said pairs contained in said common row of the matrix, wherein said timing means comprises pulse-width control means for applying both said first and sequences of pulses to both said n-type and p-type transistors of a pair when a related pixel-corresponding electrode is being accessed and for causing alternate ones of said first sequence of pulses to terminate before termination of corresponding ones of said second sequence of pulses applied to said pairs contained in said common row of the matrix, and for causing remaining ones of said first sequence of pulses to terminate after termination of corresponding ones of said second sequence of pulses applied to said pairs contained in said common row of the matrix. ### Claim 16 (depends on 15) The apparatus recited in claim 15, wherein said pulses-width control means comprises monostable multivibrator means connected to said first and second means for providing elongated pulses respectively corresponding to and having longer durations than said first and second sequences of pulses, and switching means for selecting between said first and sequences of pulses and said elongated pulses for application to corresponding n-type and p-type switching transistors of said pairs contained in said common row of the matrix.