# US 5,351,000 A · Method of cancelling offset errors in phase detectors

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- Number: US 5,351,000 A
- Document ID: US5351000A
- Status: Granted
- Kind: A
- Application number: 08/099,886
- Filed: 1993-07-30
- Granted: 1994-09-27
- Earliest claimed: 1993-07-30
- Assignees: Hughes Aircraft Company
- Inventors: William D. Farwell
- Web page: https://patentgrep.com/patent/US5351000A

## CPC

- G01R 25/00: Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
- H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A phase detector circuit which includes a first fixed delay circuit responsive to the first input signal for producing a fixedly delayed first signal which is a replica of a first input signal and delayed relative thereto by a fixed delay, a second fixed delay circuit responsive to a second input signal for producing a fixedly delayed second signal which is a replica of the second input signal and delayed relative thereto by the fixed delay, a controlled delay circuit responsive to the second input signal for producing a controllably delayed second signal and delayed relative thereto by a controlled delay, a first phase detector responsive to the fixedly delayed first signal and the adjustably delayed second signal for providing a first phase detector output that comprises the output of the phase detector circuit, a second phase detector circuit responsive to the fixedly delayed second signal and the adjustably delayed second signal for providing a second phase detector output, and an integrator responsive to the addition circuit output for controlling the controlled delay circuit to set the controlled delay such that the second phase detector output indicates zero phase error, whereby the controlled delay compensates the offset error of the first phase detector.

## Claims

### Claim 1

A phase detector circuit for comparing the phase of first and second input signals, comprising:
first fixed delay means responsive to the first input signal for producing a fixedly delayed first signal which is a replica of the first input signal and delayed relative thereto by a fixed delay;
second fixed delay means responsive to the second input signal for producing a fixedly delayed second signal which is a replica of the second input signal and delayed relative thereto by the fixed delay;
controlled delay means responsive to the second input signal for producing a controllably delayed second signal which is a replica of the second input signal and delayed relative thereto by a controlled delay;
a first phase detector responsive to said fixedly delayed first signal and said adjustably delayed second signal for providing a first phase detector output that comprises the output of the phase detector circuit;
a second phase detector responsive to said fixedly delayed second signal and said adjustably delayed second signal for providing a second phase detector output, said first and second phase detectors having substantially identical respective offset errors; and
control means responsive to said second phase detector output for controlling said controlled delay means to set said controlled delay such that said second phase detector output indicates zero phase error;
whereby said controlled delay compensates the offset error of said first phase detector.

### Claim 2 (depends on 1)

The phase detector circuit of claim 1 wherein said control means comprises an integrator.

### Claim 3 (depends on 1)

The phase detector circuit of claim 1 wherein said control means comprises:
a substraction circuit for subtracting a reference signal from the output of said second phase detector to produce a substraction circuit output, wherein the reference signal has a value that is equal to a value of the second phase detector output that indicates zero phase error; and
integrator means responsive to the subtraction circuit for producing an integrator output which controls said controlled delay means.