# US 5,350,952 A · Sample and hold circuit with push-pull output charging current > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,350,952 A - Document ID: US5350952A - Status: Granted - Kind: A - Application number: 07/909,286 - Filed: 1992-07-06 - Granted: 1994-09-27 - Earliest claimed: 1992-07-06 - Assignees: Hughes Aircraft Company - Inventors: William W. Cheng; Lloyd F. Linder - Web page: https://patentgrep.com/patent/US5350952A ## CPC - G11C 27/026: {associated with an amplifier (G11C27/028 takes precedence)} - H03K 17/667: {using complementary bipolar transistors} - H03K 2217/0036: Means reducing energy consumption - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A sample and hold circuit uses a Class AB amplifier architecture rather than a diode bridge in a sampling gate. Input and output transistor pairs (Q5, Q6; Q7, Q8) receive an input voltage (Vin) and provide at an output terminal (6) (a) an output voltage that tracks the input signal, and (b) a current from a load dependent current source (Vcc, Vee). The output current used to charge a sample holding capacitor (Ch) is not limited to the input standing current, and operates with a lower quiescent power consumption and better distortion than prior circuits. Complementary bipolar transistors (Q15, Q16, Q17, Q18; Q9, Q10, Q11, Q12) are used in a clock driver circuit and in the sampling gate to compensate for the different operating speeds of the npn and pnp transistors. ## Claims ### Claim 1 A class AB sample and hold circuit comprising: a load dependent current source, an input terminal, an output terminal, a sample gate comprising a pair of complementary bipolar input transistors that are characterized by respective standing currents and are connected to receive an input voltage signal at said input terminal, and a pair of complementary bipolar output transistors connected to provide to said output terminal (a) an output voltage signal which tracks said input signals, and (b) a current from said load dependent current source that is not limited to said input transistor standing currents, and a control circuit that actuates said input and output transistors during a track mode and deactuates said input and output transistors during a hold mode, said control circuit including a pair of bias current sources, a first pair of complementary bipolar transistors for directing the bias current source currents through respective input transistors during a track mode, a second pair of complementary bipolar transistors for diverting said bias current source currents away from said input transistors during a hold mode, and a pair of complementary emitter-follower diode circuits connected to be driven by a signal held at said output terminal substantially independent of the input signal to complete respective circuit paths for said diverted currents during a hold mode. ### Claim 2 A sample and hold circuit comprising: a load dependent current source, an input terminal, an output terminal, a sampling gate comprising a pair of input transistors connected to receive an input voltage signal at said input terminal and a pair of output transistors connected to provide to said output terminal (a) an output voltage signal which tracks said input signal, and (b) a current from said load dependent current source, and a control circuit that actuates said input and output transistors during a track mode and deactuates said input and output transistors during a hold mode, said control circuit including a pair of bias current sources, means for directing the bias current source currents through respective input transistors during a track mode, means for diverting said bias current source currents away from said input transistors during a hold mode, a pair of diode circuits connected to said sampling gate to complete respective circuit paths for said diverted currents during a hold mode, and a bootstrap circuit interconnecting said output terminal with said diode circuits to provide a diode circuit bias voltage that tracks the sampling gate output voltage, said diode circuits being configured to reverse bias said input transistors during a hold mode in response to said bias voltage. ### Claim 3 (depends on 2) The sample and hold circuit of claim 2, said diode circuit including respective buffer transistors to receive said bias voltage and buffer said output terminal from said diode circuits. ### Claim 4 (depends on 1) The sample and hold circuit of claim 1, said control circuit comprising first and second bias current sources, first and second pairs of differentially connected transistors, the first transistors of said first and second differential pairs being of opposite conductivity type to each other and connected to complete current paths for respective input transistors and bias current sources, the second transistors of said first and second differential pairs being of opposite conductivity type to each other and connected to divert said bias current source currents away from said input transistors, and a driver circuit connected to actuate the first transistors of said differential pairs during a track mode and the second transistors of said differential pairs during a hold mode. ### Claim 5 A sample and hold circuit, comprising: a load dependent current source, an input terminal, an output terminal, a sampling gate comprising a pair of input transistors connected to receive an input voltage signal at said input terminal and a pair of output transistors connected to provide to said output terminal (a) an output voltage signal which tracks said input signal, and (b) a current from said load dependent current source, and a control circuit that actuates said input and output transistors during a track mode and deactuates said input and output transistors during a hold mode, said control circuit comprising first and second bias current sources, first and second pairs of differentially connected transistors, the first transistors of said first and second differential pairs connected to complete current paths for respective input transistors and bias current sources, the second transistors of said first and second differential pairs connected to divert said bias current source currents away from said input transistors, and a driver circuit connected to actuate the first transistors of said differential pairs during a track mode and the second transistors of said differential pairs during a hold mode, said driver circuit comprising third and fourth pairs of differentially connected transistors connected to provide alternating actuating signals for the transistors of said first and second differential pairs, respectively, in response to input clock signals, the transistors of said first, second, third and fourth differential pairs comprising common-type bipolar transistors within each pair of type-npn or type-pnp, the transistors of said first differential pair being of opposite type to the transistors of said third differential pair, and the transistors of said second differential pair being of opposite type to the transistors of said fourth differential pair. ### Claim 6 (depends on 1) The sample and hold circuit of claim 1, further comprising a signal holding means connected to said output terminal to hold the output terminal voltage during a hold mode. ### Claim 7 (depends on 1) The sample and hold circuit of claim 1, said load dependent current source comprising voltage buses of opposite polarity connected in circuit with said output terminal through respective ones of said output transistors. ### Claim 8 A sample and hold circuit for applying output signals to an output terminal to which a signal holding means can be connected, comprising: positive and negative voltage buses, an input terminal, an output terminal, first and second bias current sources respectively receiving current from said positive voltage bus and delivering current to said negative voltage bus, a pnp input transistor having its base connected to said input terminal, its emitter connected to receive current from said first bias current source, and its collector connected to a negative voltage bus, an npn input transistor having its base connected to said input terminal, its emitter connected to deliver current to said second bias current source, and it collector connected to a positive voltage bus, an npn output transistor having its base connected to the emitter of said pnp input transistor, its emitter connected to said output terminal and its collector connected to receive a current to supply to said output terminal during a track mode, a pnp output transistor having its base connected to the emitter of said npn input transistor, its emitter connected to said output terminal and its collector connected to transmit a current received from said output terminal during a track mode, and a control circuit connected to divert current from said bias current sources away from said input transistors during a hold mode. ### Claim 9 (depends on 8) The sample and hold circuit of claim 8, wherein the collectors of said npn and pnp output transistors are connected respectively to positive and negative voltage buses. ### Claim 10 (depends on 9) The sample and hold circuit of claim 9, wherein said output transistors are scaled larger than said input transistors, and thereby provide current amplification with respect to the currents through said input transistors during a track mode. ### Claim 11 (depends on 9) The sample and hold circuit of claim 9, said control circuit including first and second pairs of differentially connected transistors, a pair of current diversion circuits, and a driver circuit connected to actuate the first transistors of said differential pairs during a track mode and the second transistors of said differential pairs during a hold mode, the first transistors of said first and second differential pairs connected to complete respective current paths for said first and second bias current sources and for said pnp and npn input transistors, and the second transistors of said first and second differential pairs connected to complete respective current paths for said first and second bias current sources and for respective current diversion circuits. ### Claim 12 (depends on 11) The sample and hold circuit of claim 11, said driver circuit comprising third and fourth pairs of differentially connected transistors connected to provide alternating actuating signals for the transistors of said first and second differential pairs, respectively, in response to input clock signals, the transistors of said first, second, third and fourth differential pairs comprising common-type bipolar transistors within each pair of type-npn or type-pnp, the transistors of said first differential pair being of opposite type to the transistors of said third differential pair, and the transistors of said second differential pair being of opposite type to the transistors of said fourth differential pair. ### Claim 13 (depends on 11) The sample and hold circuit of claim 11, said current diversion circuits comprising a first diversion transistor connected in series with at least one respective diode to transmit current from a positive voltage bus to the second transistor of said second differential pair when the latter transistor is actuated, and a second diversion transistor connected in series with at least one respective diode to transmit current from the second transistor of said first differential pair to a negative voltage bus when the latter transistor is actuated. ### Claim 14 (depends on 13) The sample and hold circuit of claim 13, said first and second diversion transistors comprising bipolar transistors with their collector-emitter circuits connected between their respective voltage buses and their respective diodes, and their bases connected to track the output terminal voltage, said diversion transistors buffering the output terminal from their respective diodes. ### Claim 15 (depends on 8) The sample and hold circuit of claim 8, further comprising a signal holding means connected to said output terminal to hold the output terminal voltage during a hold mode. ### Claim 16 A balanced control circuit for providing alternating circuit connections in response to alternating control signals, comprising: a first pair of differentially connected bipolar transistors of a common type that is either type-npn or type-pnp, a second pair of differentially connected bipolar transistors of a common type that is opposite to that of the first differential pair, respective output circuits connected to the transistors of said second differential pair for generating an alternating pair of bias signals in response to alternating control signals applied to the transistors of said second differential pair, and means for applying said bias signals to alternately actuate and deactuate the transistors of said first differential pair. ### Claim 17 (depends on 16) The control circuit of claim 16, for providing alternating push-pull circuit connections in response to said alternating control signals, further comprising a third pair of differentially connected bipolar transistors of a common type that is opposite to said first differential pair, a fourth pair of differentially connected bipolar transistors of a common type that is opposite to said second differential pair, respective output circuits connected to the transistors of said fourth differential pair for generating an alternating pair of bias signals in response to alternating control signals applied to the transistors of said fourth differential pair, the first and second transistors of said first differential pair connected in series respectively with the second and first transistors of said third differential pair, means for applying alternating control signals to the transistors of said fourth differential pair in synchronism with the application of alternating control signals to the transistors of said second differential pair, and means for applying the bias signals from the output circuits for said fourth differential pair to respective transistors of said third differential pair so that the first transistors of said first and third differential pairs are alternately actuated and deactuated in synchronism with each other, and the second transistors of said first and third differential pairs are alternately actuated and deactuated in synchronism with each other and opposite to the actuation and deactuation of said first transistors. ### Claim 18 (depends on 6) The sample and hold circuit of claim 6, said signal holding means comprising a capacitor that is connected to said output terminal through a resistor.