# US 5,350,942 A · Low resistance silicided substrate contact

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- Number: US 5,350,942 A
- Document ID: US5350942A
- Status: Granted
- Kind: A
- Application number: 08/104,386
- Filed: 1993-08-09
- Granted: 1994-09-27
- Earliest claimed: 1990-04-02
- Assignees: National Semiconductor Corporation
- Inventors: Rick C. Jerome; Frank Marazita
- Web page: https://patentgrep.com/patent/US5350942A

## CPC

- H10W 20/021: {of interconnections within wafers or substrates}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.

## Claims

### Claim 1

In an integrated circuit a substrate contact comprising:
a p+ doped channel stop region formed in a substrate and spaced apart from a top surface of said substrate;
a p+ doped extrinsic region located within the substrate adjacent a top surface of said substrate and contacting said channel stop region;
a first p+ doped polysilicon region formed on the top surface of said substrate adjacent said p+ doped extrinsic region;
a second p+ doped polysilicon region formed on the top surface of said substrate adjacent said first p+ doped extrinsic region, and spaced from said first p+ doped polysilicon region;
an oxide layer formed on the top surface of the substrate and spanning a distance between said first and said second p+ doped polysilicon regions; and
said p+ doped extrinsic region including an extended region located under said oxide layer and extending deeper into said channel stop region than a remaining portion of said p+ doped extrinsic region.

### Claim 2 (depends on 1)

A substrate contact, as claimed in claim 1, further comprising:
refractory metal silicide contacting said first p+ doped polysilicon region.

### Claim 3 (depends on 2)

An integrated circuit, as .claimed in claim 2, wherein said refractory metal contacts said first p+ doped extrinsic region.

### Claim 4 (depends on 2)

An integrated circuit, as claimed in claim 2, wherein said refractory metal contacting said first p+ doped polysilicon region is spaced from a second refractory metal contacting said second p+ doped polysilicon region.