# US 5,350,662 A · Maskless process for forming refractory metal layer in via holes of GaAs chips

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- Number: US 5,350,662 A
- Document ID: US5350662A
- Status: Granted
- Kind: A
- Application number: 08/181,371
- Filed: 1994-01-13
- Granted: 1994-09-27
- Earliest claimed: 1992-03-26
- Assignees: Hughes Aircraft Company
- Inventors: Tom Y. Chi
- Web page: https://patentgrep.com/patent/US5350662A

## CPC

- H10P 76/2041: {Photolithographic processes}
- G03F 7/2022: {Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A "maskless" process is provided for the formation of a refractory metal layer (22b), such as titanium, in via holes (18) through GaAs wafers (12) to contact microwave monolithic integrated circuit (MMIC) devices (10) formed on the front surface (12a) thereof. The process of the invention, which prevents AuSn solder (28) from filling up the holes during a subsequent eutectic AuSn bonding of the device to a metal carrier (30), such as molybdenum, utilizes the difference of resist thickness on the GaAs backside surface (12b) and in the via holes, so that the resist (24b) remaining in the via holes after removing the resist (24a) over the GaAs back surface serves as a mask in etching the refractory metal layer (22a) over the GaAs back surface. The process of the invention does not require any masks, and results in self-alignment of the refractory metal to the via hole. The process is simple and results in high yield of the MMIC devices on GaAs chips (26).

## Claims

### Claim 1

A method for providing contacts to microwave monolithic integrated circuit devices formed on a gallium arsenide wafer, said gallium arsenide wafer having a front and a back surface wherein (1) at least one via hole is formed from said back surface of said wafer through to said front surface of said wafer to expose a portion of each said device, (2) a metal layer is formed on said back surface and in each of said via holes, thereinto (3),each of said devices subsequently bonded to a metal carrier using a AuSn solder alloy, contacting said portion of each said device, said method comprising the steps of:
(a) forming a layer of a refractory metal lining each of said via holes,
(b) blanket-depositing a layer of said refractory metal on said metal layer, including in said via holes;
(c) forming a positive resist layer on said refractory metal layer and filling said via holes with said resist layer;
(d) baking said resist layer;
(e) exposing all of said resist layer to ultraviolet radiation in the absence of any mask layer;
(f) developing said resist layer to remove all of said resist layer lying over said back surface, leaving said resist layer in said via holes to thereby uncover portions of said refractory metal layer over said back surface;
(g) removing said uncovered portions of refractory metal over said back surface; and
(h) removing said resist layer remaining in said via holes, leaving said refractory metal lining said via holes, wherein said refractory metal layer is selfaligned to said via holes to prevent the intrusion of said AuSn solder.

### Claim 2 (depends on 1)

The method of claim 1 wherein said metal layer comprises a multilayer structure consisting of a first layer of titanium formed on said gallium arsenide back surface, a second layer of platinum formed on said first layer of titanium, and a third layer of gold formed on said second layer of platinum.

### Claim 3 (depends on 1)

The method of claim 1 wherein said refractory metal comprises a metal selected from the group consisting of titanium, tungsten, tantalum, and alloys thereof.

### Claim 4 (depends on 3)

The method of claim 3 wherein said refractory metal is deposited to a thickness ranging from about 100 to 2,000 .ANG..

### Claim 5 (depends on 3)

The method of claim 3 wherein said refractory metal consists essentially of titanium formed to a thickness of about 500 to 2,000 .ANG..

### Claim 6 (depends on 5)

The method of claim 5 wherein said thickness is about 1,000 .ANG..

### Claim 7 (depends on 1)

The method of claim 1 wherein said resist is deposited to a thickness of about 1 .mu.m over the back surface of said gallium arsenide wafer and said via hole is about 50 to 100 .mu.m in depth.

### Claim 8 (depends on 1)

The method of claim 1 wherein said wafer is subsequently diced into chips, each chip carrying at least one of said microwave monolithic integrated circuit devices, and each said chip is mounted on said metal carrier using eutectic gold-tin solder.

### Claim 9

A process for providing contacts to microwave monolithic integrated circuit devices formed on a gallium arsenide wafer, said gallium arsenide wafer having a front surface and a back surface wherein (1) at least one via hole is formed from said back surface of said wafer through to said front surface to expose a portion of each said device, (2) a metal layer consisting essentially of a titanium/platinum/gold multistructure is formed on said back surface and in each of said via holes, contacting said portion of said device, and (3) each said device is subsequently bonded to a metal carrier using a AuSn solder alloy, wherein said process comprises, prior to step (3):
(a) blanket-depositing a layer of titanium ranging from about 500 to 1,000 .ANG. in thickness on said metal layer, including in said via holes;
(b) forming a positive resist layer on said titanium layer and filling said via holes;
(c) baking said resist layer;
(d) exposing all of said resist layer to ultraviolet radiation in the absence of any mask layer;
(e) developing said resist to remove all resist lying over said back surface but leaving resist in said via holes to thereby uncover portions of said titanium layer over said back surface;
(f) removing said uncovered portions of titanium over said back surface; and
(g) removing said resist remaining in said via holes, leaving said titanium lining said via holes, wherein said titanium layer is self-aligned to said via hole to prevent the intrusion of said AuSn solder thereinto.

### Claim 10 (depends on 9)

The process of claim 9 wherein said thickness of said titanium layer is about 1,000 .ANG..

### Claim 11 (depends on 9)

The process of claim 9 wherein said resist is deposited to a thickness of about 0.5 to 5 .mu.m over the back surface of said gallium arsenide wafer and said via hole is about 50 to 100 .mu.m in depth.

### Claim 12 (depends on 9)

The process of claim 9 wherein said wafer is subsequently diced into chips, each chip carrying at least one of said microwave monolithic integrated circuit devices, and each said chip is mounted on said metal carrier using eutectic gold-tin solder.