# US 5,350,486 A · Semiconductor planarization process

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- Number: US 5,350,486 A
- Document ID: US5350486A
- Status: Granted
- Kind: A
- Application number: 08/065,122
- Filed: 1993-05-20
- Granted: 1994-09-27
- Earliest claimed: 1991-10-10
- Assignees: SGS-Thomson Microelectronics S.A.
- Inventors: Kuei-Wu Huang
- Web page: https://patentgrep.com/patent/US5350486A

## CPC

- H10P 95/066: {the removal being a selective chemical etching step, e.g. selective dry etching through a mask}
- H10W 20/092: {by smoothing the dielectric parts}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for planarizing an integrated circuit structure having a glass layer overlying an oxide layer of an integrated circuit is presented. The method includes the steps of selectively etching portions of the glass structure that overlie portions of the oxide layer that have higher elevations than other portions of the oxide layer, and then etching the glass layer overall. The etching step includes forming a layer of photoresist over the glass layer, exposing selected areas of the photoresist over the portions of the oxide layer that have higher elevations than other portions of the oxide layer, removing the exposed areas of the photoresist, and etching the glass layer within the removed areas of the photoresist. The mask used in patterning the photoresist can be the same mask, or its negative, that is used in forming the metalization layer over which the oxide and glass layers have been formed. Additionally, an integrated circuit structure is presented that includes a substrate in which integrated circuit elements are constructed, a first interconnection metalization over the substrate interconnecting selected ones of the integrated circuit elements, and an oxide layer over the substrate and the first metal interconnection pattern. A glass layer over the oxide layer is substantially planar between portions that overlie the metalization and portions that do not over lie the metalization.

## Claims

### Claim 1

A method for planarizing an integrated circuit structure having a isolating layer overlying an oxide layer of an integrated circuit, comprising:
forming a layer of photoresist over said isolating layer;
exposing selected areas of said photoresist over portions of said oxide layer that have higher elevations than other portions of said oxide layer;
removing said exposed areas of said photoresist;
at least partially etching said isolating layer that is within said removed areas of said photoresist;
removing said layer of photoresist;
and etching said isolating layer overall.

### Claim 2 (depends on 1)

The method of claim 1 wherein said oxide layer has been deposited by plasma-enhanced oxide deposition techniques.

### Claim 3 (depends on 1)

The method of claim 1 wherein said isolating layer has been formed by spin-on glass techniques.

### Claim 4 (depends on 1)

The method of claim 1 further comprising providing metal layers under said oxide.

### Claim 5 (depends on 4)

The method of claim 4 wherein said step of exposing selected areas of said photoresist over said portions of said oxide layer that overlie said metal layers comprises providing a mask that is a negative of a mask used to form said metal layers, and exposing said layer of photoresist through said mask.

### Claim 6 (depends on 4)

The method of claim 4 wherein said step of forming a layer of photoresist over said isolating layer comprises forming a layer of positive resist over said isolating layer, and wherein said step of exposing selected areas of said photoresist over said portions of said oxide layer that overlie said metal layers comprises utilizing a mask that was used to form said metal layers, and exposing said layer of photoresist through said mask.

### Claim 7

A method for manufacturing an integrated circuit, comprising:
providing a substrate;
forming a first metal interconnection pattern over said substrate for interconnecting selected components of said integrated circuit;
forming an oxide layer over said substrate and said first metal interconnection pattern;
forming a layer of glass over said oxide layer;
selectively etching portions of said glass and oxide layers that overlie said metal interconnection pattern;
and etching said glass layer overall.

### Claim 8 (depends on 7)

The method of claim 7 wherein said step of forming an oxide layer over said substrate and said first metal interconnection pattern comprises forming CVD oxide over said substrate and said first metal interconnection pattern.

### Claim 9 (depends on 8)

The method of claim 8 wherein said step of forming a layer of glass over said oxide layer comprises forming a layer of spin-on glass over said oxide layer.

### Claim 10 (depends on 9)

The method of claim 9 wherein said step of selectively etching portions of said glass comprises forming a layer of photoresist over said glass layer, exposing selected areas of said photoresist over said first metal interconnection pattern, removing said exposed areas of said photoresist, and etching said glass and oxide layers within said removed areas of said photoresist.

### Claim 11 (depends on 10)

The method of claim 10 wherein said step of etching said glass and oxide layers within said removed areas of said photoresist comprises etching between about 10 and 90 percent of the thickness of said glass and oxide layers within said removed areas.

### Claim 12 (depends on 10)

The method of claim 10 wherein said step of forming a layer of photoresist comprises forming a layer of positive photoresist, and wherein said step of exposing selected areas of said photoresist over said first metal interconnection pattern comprises providing a mask that is a negative of a mask used to form said metal layers, and exposing said layer of photoresist through said mask.

### Claim 13 (depends on 10)

The method of claim 10 wherein said step of forming a layer of photoresist comprises forming a layer of negative photoresist, and wherein said step of exposing selected areas of said photoresist over said first metal interconnection pattern comprises providing a mask used to form said metal layers, and exposing said layer of photoresist through said mask.

### Claim 14 (depends on 10)

The method of claim 10 further comprising forming a second level of metal on the glass layer.

### Claim 15 (depends on 11)

The method of claim 11 wherein said step of etching between about 10 and 90 percent of the thickness of said glass and oxide layers within said removed areas comprises etching between about 33 and 66 percent of the thickness of said glass and oxide layers within said removed areas.