# US 5,349,683 A · Bidirectional FIFO with parity generator/checker

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- Number: US 5,349,683 A
- Document ID: US5349683A
- Status: Granted
- Kind: A
- Application number: 07/916,304
- Filed: 1992-07-16
- Granted: 1994-09-20
- Earliest claimed: 1992-07-16
- Assignees: Mosel Vitelic, Inc.
- Inventors: Sheau-Dong Wu; Hiro Yoshida
- Web page: https://patentgrep.com/patent/US5349683A

## CPC

- G06F 5/065: {Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's}
- G06F 13/4018: {with data-width conversion}
- G06F 2205/067: Bidirectional FIFO, i.e. system allowing data transfer in two directions
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A bidirectional first-in first-out buffer device including on a single chip a single bank FIFO memory array, two bidirectional input/output ports, an input multiplexer for selecting which port to input data from, an output multiplexer for selecting which port to output data to, a byte/word converter for converting input data from a byte format to a word format, a word/byte converter for converting output data from a word format to a byte format, a parity generator/checker for generating parity output signals or confirming parity input signals, a flag generator for generating empty/full and half full flags, and control logic for controlling the direction, format and timing of data flow. The device is packaged in a 52-pin plastic leaded chip carrier package.

## Claims

### Claim 1

A single chip integrated circuit bidirectional memory buffer device comprising:
a first bidirectional data port;
a second bidirectional data port;
an input multiplexer responsive to a first control signal, wherein when said first control signal is of a first state:
said input multiplexer is operative to receive a series of data words from said first bidirectional data port, and output said data words;
and when said first control signal is of a second state:
said input multiplexer is operative to receive a series of data words from said second bidirectional data port, and output said data words;
a byte/word converter responsive to a second control signal, wherein when said second control signal is of a first state:
said byte/word converter is operative to receive a set of input data words, each x-bits in length, from the input mux, to construct an assembled data word, y-bits in length, where y is greater than x, by concatenating the bits of the set of input data words, and to output said assembled data word;
and when said second control signal is of a second state:
said byte/word converter is operative to receive input data words, y-bits in length, from the input mux, and output said input data words unchanged in length;
a FIFO memory array responsive to a third control signal, wherein upon receipt of said third signal:
said FIFO memory array is operative to receive a data word from the byte/word converter, to write said data word into a memory location indicated by a write pointer, and to update said write pointer to indicate the next memory location available to be written to;
said FIFO memory array further responsive to a fourth control signal, wherein upon receipt of said fourth signal:
said FIFO memory array is operative to read a data word from a memory location indicated by a read pointer, to output said data word, and to update said read pointer to indicate the location of the next data word to be read;
a word/byte converter responsive to a fifth control signal, wherein when said fifth control signal is of a first state:
said word/byte converter is operative to receive a data word from the FIFO memory array, to construct a set of disassembled data words, each containing a part of the received data word, and to output said disassembled data words;
and when said fifth control signal is of a second state:
said word/byte converter is operative to receive data words from the FIFO memory array, and to output said data words unchanged;
an output mux, responsive to a sixth control signal, wherein when said sixth control signal is of a first state:
said output multiplexer is operative to receive a series of data words from said word/byte converter, and to output said data words to said first bidirectional data port;
and when said sixth control signal is of a second state:
said output multiplexer is operative to receive a series of data words from said word/byte converter, and to output said data words to said second bidirectional data port;
control logic responsive to external input signals, and operative to generate said first, second, third, fourth, fifth and sixth control signals.

### Claim 2 (depends on 1)

A single chip integrated circuit bidirectional memory buffer device as recited in claim 1, further comprising:
a parity generator/checker responsive to a seventh control signal, wherein when said seventh control signal is of a first state:
said parity generator/checker is operative to receive an input data word from the input multiplexer, to compute a set of parity values corresponding to the input data word, to compare the set of parity values to a set of parity inputs, and to output a parity error flag if the set of parity values does not equal the set of parity inputs;
and when said seventh control signal is of a second state:
said parity generator/checker is operative to receive an output data word from the FIFO memory array, and to generate a set of parity outputs corresponding to the output data word;
and wherein said control logic is further operative to generate said seventh control signal.

### Claim 3 (depends on 1)

A single chip integrated circuit bidirectional memory buffer device as recited in claim 1 wherein said device is packaged in a 52-pin plastic leaded chip carrier package.

### Claim 4 (depends on 2)

A single chip integrated circuit bidirectional memory buffer device as recited in claim 2 wherein said device is packaged in a 52-pin plastic leaded chip carrier package.

### Claim 5

A bidirectional high speed buffered digital communication system comprising:
a first high speed digital transceiver;
a second high speed digital transceiver;
a bidirectional memory buffer device including:
a first bidirectional data port communicatively connected to said first transceiver;
a second bidirectional data port communicatively connected to said second transceiver;
an input multiplexer responsive to a first control signal,
wherein when said first control signal is of a first state:
said input multiplexer is operative to receive a series of data words from said first bidirectional data port, and output said data words;
and when said first control signal is of a second state:
said input multiplexer is operative to receive a series of data words from said second bidirectional data port, and output said data words;
a byte/word converter responsive to a second control signal, wherein when said second control signal is of a first state:
said byte/word converter is operative to receive a set of input data words, each x-bits in length, from the input mux, to construct an assembled data word, y-bits in length, where y is greater than x, by concatenating the bits of the set of input data words, and to output said assembled data word;
and when said second control signal is of a second state:
said byte/word converter is operative to receive input data words, y-bits in length, from the input mux, and output said input data words unchanged in length;
a FIFO memory array responsive to a third control signal, wherein upon receipt of said third signal:
said FIFO memory array is operative to receive a data word from the byte/word converter, to write said data word into a memory location indicated by a write pointer, and to update said write pointer to indicate the next memory location available to be written to;
said FIFO memory array further responsive to a fourth control signal, wherein upon receipt of said fourth signal:
said FIFO memory array is operative to read a data word from a memory location indicated by a read pointer, to output said data word, and to update said read pointer to indicate the location of the next data word to be read;
a word/byte converter responsive to a fifth control signal, wherein when said fifth control signal is of a first state:
said word/byte converter is operative to receive a data word from the FIFO memory array, to construct a set of disassembled data words, each containing a part of the received data word, and to output said disassembled data words;
and when said fifth control signal is of a second state:
said word/byte converter is operative to receive data words from the FIFO memory array, and to output said data words unchanged;
an output mux, responsive to a sixth control signal, wherein when said sixth control signal is of a first state:
said output multiplexer is operative to receive a series of data words from said word/byte converter, and to output said data words to said first bidirectional data port;
and when said sixth control signal is of a second state:
said output multiplexer is operative to receive a series of data words from said word/byte converter, and to output said data words to said second bidirectional data port;
control logic responsive to external input signals, and operative to generate said first, second, third, fourth, fifth and sixth control signals.

### Claim 6 (depends on 5)

A bidirectional high speed buffered digital communication system as recited in claim 5, wherein said bidirectional memory buffer device further includes:
a parity generator/checker responsive to a seventh control signal, wherein when said seventh control signal is of a first state:
said parity generator/checker is operative to receive an input data word from the input multiplexer, to compute a set of parity values corresponding to the input data word, to compare the set of parity values to a set of parity inputs, and to output a parity error flag if the set of parity values does not equal the set of parity inputs;
and when said seventh control signal is of a second state:
said parity generator/checker is operative to receive an output data word from the FIFO memory array, and to generate a set of parity outputs corresponding to the output data word;
and wherein said control logic is further operative to generate said seventh control signal.