# US 5,349,608 A · Viterbi ACS unit with renormalization

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- Number: US 5,349,608 A
- Document ID: US5349608A
- Status: Granted
- Kind: A
- Application number: 08/038,323
- Filed: 1993-03-29
- Granted: 1994-09-20
- Earliest claimed: 1993-03-29
- Assignees: Stanford Telecommunications, Inc.
- Inventors: Hatch Graham; Christine Nguyen
- Web page: https://patentgrep.com/patent/US5349608A

## CPC

- H03M 13/4107: {implementing add, compare, select [ACS] operations}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

In a Viterbi decoder including an add-compare-select (ACS) processor, speed is enhanced without loss of performance by maintaining a dynamic cumulative metric range for computed state metrics. Current state metrics are added to new branch metrics to obtain two computed metrics, and the smaller of the two computed metrics is stored along with previously computed state metrics. The stored state metrics are compared with a selected scale factor, for example one-half maximum scale factor, and all current state metrics are rescaled when the minimum stored metric value exceeds the selected scale factor.

## Claims

### Claim 1

An add-compare-select (ACS) processor for use in Viterbi decoding of convolutional codes comprising a plurality of ACS elements, each element including
first and second adders to add values of current state metrics to new branch metrics for an upper and a lower branch, a comparator coupled to said adders for selecting the smaller of two metrics, and a storage element for storing the selected metric; and
renormalization means for comparing stored metrics with a selected scale factor in one clock cycle, and rescaling all stored metrics when the minimum stored metric value exceeds said selected scale factor in the following clock cycle.

### Claim 2 (depends on 1)

The add-compare-select (ACS) processor as defined by claim 1 wherein said processor includes 64 ACS elements with the cumulative path metrics being 6 bits wide, the maximum scale factor being 63 and said renormalization means rescaling all stored metrics when the minimum stored metric value exceeds a selected scale factor of 31.

### Claim 3

In a Viterbi decoder using an add-compare-select processor for determining minimum path metrics, a method of maintaining dynamic cumulative metric range including the steps of
adding current state metrics to new branch metrics for upper and lower branches to obtain two computed metrics,
selecting the smaller of said two computed metrics,
storing said smaller of said two metrics along with other current state metrics,
comparing said current state metrics with a selected scale factor during one clock cycle, and
rescaling said current state metrics when the minimum stored metric value exceeds said selected scale factor in the following clock cycle.