# US 5,349,563 A · Mask ROM

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- Number: US 5,349,563 A
- Document ID: US5349563A
- Status: Granted
- Kind: A
- Application number: 08/041,587
- Filed: 1993-04-05
- Granted: 1994-09-20
- Earliest claimed: 1992-04-03
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Taira Iwase
- Web page: https://patentgrep.com/patent/US5349563A

## CPC

- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 17/126: {Virtual ground arrays}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A mask ROM having a plurality of memory cell blocks, each composed of a main bit line, a ground line, and a plurality of memory cells for storing information. The mask ROM also includes a sense amplifier for reading the information stored in the memory cells via the main bit line. The mask ROM has a plurality of first block selecting means for selecting a memory cell block connected to the main bit line from a plurality of the memory cell blocks and a plurality of second block selecting means for selecting a memory cell block connected to the ground line from a plurality of the memory cell blocks. The first and second block selecting means are arranged alternately, with the memory cell block sandwiched therebetween.

## Claims

### Claim 1

A mask ROM having a plurality of memory cell blocks each composed of a main bit line, a ground line, and a plurality of memory cells for storing information; and a sense amplifier for reading the information stored in the memory cells via the main bit line, which comprises:
a plurality of first block selecting means for selecting a memory cell block to be connected to the main bit line from a plurality of the memory cell blocks; and
a plurality of second block selecting means for selecting a memory cell block to be connected to the ground line from a plurality of the memory cell blocks, said first and second block selecting means being arranged alternately with the memory cell block sandwiched therebetween.

### Claim 2 (depends on 1)

The mask ROM of claim 1, wherein said first and second block selecting means are shared by adjacent memory cell blocks.

### Claim 3 (depends on 2)

The mask ROM of claim 2, which further comprises switching means connected between the main bit line and a plurality of said memory cell blocks, for connecting the main bit line to the selected memory cell block in response to a select command given by said first block selecting means.

### Claim 4 (depends on 1)

The mask ROM of claim 1, which further comprises a plurality of bit lines connected to a plurality of the memory cells, respectively; and a plurality of word lines arranged so as to intersect the bit lines, for specifying a memory cell from a plurality of the memory cells in cooperation with the bit lines.

### Claim 5 (depends on 4)

The mask ROM of claim 4, wherein a plurality of the memory cells are a plurality of transistors each having a source region and a drain region at intersections between the bit line and the word line and a channel region sandwiched between the intersections.