# US 5,349,555 A · Redundancy circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,349,555 A - Document ID: US5349555A - Status: Granted - Kind: A - Application number: 08/052,629 - Filed: 1993-04-27 - Granted: 1994-09-20 - Earliest claimed: 1992-05-07 - Assignees: Mitsubishi Denki Kabushiki Kaisha - Inventors: Michio Nakajima - Web page: https://patentgrep.com/patent/US5349555A ## CPC - G11C 29/781: {combined in a redundant decoder} - G11C 29/785: {with redundancy programming schemes} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In order to obtain a redundancy circuit which can freely arrange its fuse in a required position with disciplined accessibility after employment, a combination circuit (50) receives outputs (QA0 to QA7) obtained by decoding a column address (AXM) by a column line decoder (2), signals (QB0 to QB7) indicating a faulty line, signals (L0 to L7) generated from the signals (QB0 to QB7) and an inverted signal (ENB*), to generate signals (YS0 to YS8) for controlling selecting switches for specifying column lines. If a K-th column line is faulty, a column line selecting switch for selecting the K-th column line is forcibly turned off and an (N+1)-th column line is allocated with respect to specification of an N-th column line (N.gtoreq.K). Thus, fuse positions of redundancy circuits can be standarlized between products so that the products can be easily mass-produced and supplied at a low cost even if the redundancy circuits are contained in small quantities of various ASICs. ## Claims ### Claim 1 A redundancy circuit comprising: (a) storage means having (M+N) storage columns including M specific redundant columns, each said storage column being substantially formed by a plurality of storage units; (b) faulty column specifying means for outputting a faulty column signal indicating J faulty columns being storage columns having faulty said storage units; (c) column signal specifying means for outputting a column signal indicating specific one of said storage columns and a match signal indicating match/mismatch of said specific one of storage columns and said faulty columns; (d) a combination circuit receiving said column signal, said faulty column signal and said match signal for specifying one of .said specific redundant columns in correspondence to said specific one of storage columns when said specific one of storage columns is a faulty column; and (e) an enable circuit for generating an enable signal for controlling the operation of said combination circuit, where M and N represent positive integers and J (.ltoreq.M) represents a non-negative integer. ### Claim 2 (depends on 1) A redundancy circuit in accordance with claim 1, wherein said storage means has equal numbers of said storage units in respective said storage columns, and is arranged in the form of a matrix. ### Claim 3 (depends on 1) A redundancy circuit in accordance with claim 1, wherein said faulty column specifying means comprises: (b-1) original faulty column signal generation means for outputting an original faulty column signal, and (b-2) faulty column signal conversion means for converting said original faulty column signal to said faulty column signal, and said column signal specifying means comprises: (c-1) an input terminal for receiving an original column signal, (c-2) column signal conversion means for converting said original column signal to said column signal, and (c-3) match detection means for receiving said original column signal and said original faulty column signal and generating said match signal. ### Claim 4 (depends on 3) A redundancy circuit in accordance with claim 3, wherein both of said integers M and J are 1. ### Claim 5 (depends on 4) A redundancy circuit in accordance with claim 4, wherein said original faulty column generation means is substantially formed by a plurality of fuse circuits having fuses respectively for defining said original faulty column signal by conduction/non-conduction of said fuses. ### Claim 6 (depends on 5) A redundancy circuit in accordance with claim 5, wherein said combination circuit has a logical element for taking the logical sum of said match signal and said enable signal, the output of said logical element specifying said redundant columns. ### Claim 7 (depends on 3) A redundancy circuit in accordance with claim 3, further comprising activation means for activating said storage columns of said storage means being specified by said combination circuit. ### Claim 8 (depends on 3) A redundancy circuit in accordance with claim 3, wherein said enable circuit includes a fuse being arranged in the exterior of the pattern layout of said storage means for defining said enable signal by conduction/non-conduction of said fuse. ### Claim 9 A redundancy circuit comprising: (a) storage means having (M+N) storage columns including M redundant columns, each said storage column being substantially formed by a plurality of storage units; (b) faulty column specifying means for outputting a faulty column signal indicating J faulty columns being storage columns having faulty said storage units; (c) column signal specifying means for outputting a column signal indicating a K-th said storage column; (d) a combination circuit receiving said column signal and said faulty column signal for newly sequencing first to (N+J)-th said storage columns excluding said J faulty columns as first to N-th columns in order from the low numbered one and specifying the new K-th storage column; and (e) an enable circuit for generating an enable signal for controlling the operation of said combination circuit, where M, N and K (.ltoreq.M) represent positive integers and J (.ltoreq.M) represents a non-negative integer. ### Claim 10 (depends on 9) A redundancy circuit in accordance with claim 9, wherein said storage means has equal numbers of said storage units in respective said storage columns, and is arranged in the form of a matrix. ### Claim 11 (depends on 9) A redundancy circuit in accordance with claim 9, wherein said faulty column specifying means comprises: (b-1) original faulty column signal generation means for outputting an original faulty column signal, and (b-2) faulty column signal conversion means for converting said original faulty column signal to said faulty column signal. ### Claim 12 (depends on 11) A redundancy circuit in accordance with claim 11, wherein said original faulty column signal generation means is substantially formed by a plurality of fuse circuits having fuses respectively for defining said original faulty column signal by conduction/non-conduction of respective said fuses. ### Claim 13 (depends on 11) A redundancy circuit in accordance with claim 11, wherein said column signal specifying means comprises: (c-1) an input terminal for receiving an original column signal, and (c-2) column signal conversion means for converting said original column signal to said column signal. ### Claim 14 (depends on 9) A redundancy circuit in accordance with claim 9, wherein both of said integers M and J are 1. ### Claim 15 (depends on 14) A redundancy circuit in accordance with claim 14, wherein said combination circuit comprises: (d-1) specifying means for outputting first to (N+1)-th specifying signals corresponding to said first to (N+1)-th storage columns respectively and taking binary logics, said specifying signals being lower-numbered as compared with those corresponding to said faulty columns are inverted in logical value as compared with remaining said specifying signals. ### Claim 16 (depends on 14) A redundancy circuit in accordance with claim 14, further comprising activation means for activating said storage columns of said storage means being specifyed by said combination circuit. ### Claim 17 (depends on 14) A redundancy circuit in accordance with claim 14, wherein said enable circuit includes a fuse being arranged in the exterior of the pattern layout of said storage means for defining said enable signal by conduction/non-conduction of said fuse.