# US 5,349,548 A · Non-integral delay circuit

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- Number: US 5,349,548 A
- Document ID: US5349548A
- Status: Granted
- Kind: A
- Application number: 08/061,358
- Filed: 1993-05-13
- Granted: 1994-09-20
- Earliest claimed: 1992-06-26
- Assignees: U.S. Philips Corporation
- Inventors: Antonius H. H. J. Nillesen
- Web page: https://patentgrep.com/patent/US5349548A

## CPC

- H03H 17/0027: {by means of a non-recursive filter}
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

A non-integral delay circuit for delaying a digital signal by a selectable fraction (.delta.) of a sampling period of the digital signal includes a first differentiator (S3) to obtain a first differential signal (F1) having a first phase characteristic with respect to the digital signal, a second differentiator (D) to obtain a second differential signal (F2) having a second phase characteristic with respect to the digital signal, the first and second phase characteristics differing from each other, a mixer (MIX) for combining the first (F1) and second (F2) differential signals in dependence on the selectable fraction (.delta.) to obtain a phase-adjusted correction signal, and an adder (A9) which adds a product (M3) of the selectable fraction (.delta.) and the phase-adjusted correction signal to the digital signal, to obtain the digital signal delayed by the selectable fraction (.delta.) of the sampling period of the digital signal.

## Claims

### Claim 1

A non-integral delay circuit for delaying a digital signal by a selectable fraction (.delta.) of a sampling period of said digital signal, comprising:
first means for differentiating said digital signal to obtain a first differential signal (F1) having a first phase characteristic with respect to said digital signal;
second means for differentiating said digital signal to obtain a second differential signal (F2) having a second phase characteristic with respect to said digital signal; said first and second phase characteristics differing from each other;
means for combining said first (F1) and second (F2) differential signals in dependence on said selectable fraction (.delta.) to obtain a phase-adjusted correction signal; and
means for adding a product of said selectable fraction (.delta.) and said phase-adjusted correction signal to said digital signal, to obtain said digital signal delayed by said selectable fraction (.delta.) of the sampling period of said digital signal.

### Claim 2 (depends on 1)

A non-integral delay circuit as claimed in claim 1, wherein said combining means include a mixer circuit for multiplying said first differential signal (F1) by a linearly increasing function of said selectable fraction (.delta.) and for multiplying said second differential signal (F2) by a linearly decreasing function of said selectable fraction (.delta.).

### Claim 3 (depends on 1)

A non-integral delay circuit as claimed in claim 1, wherein said first differentiating means include a subtracter for subtracting each time two successive samples of said digital signal, and wherein said second differentiating means include a filter having an asymmetrical impulse response.

### Claim 4 (depends on 1)

A non-integral delay circuit as claimed in claim 1, wherein said first differentiating means include a filter coupled to receive said digital signal to furnish an interpolated signal, and a subtracter for subtracting said interpolated signal and said digital signal from each other.

### Claim 5 (depends on 1)

A non-integral delay circuit as claimed in claim 1, wherein said first and second differentiating means have substantially corresponding amplitude characteristics.

### Claim 6 (depends on 1)

A non-integral delay circuit as claimed in claim 1, wherein said combining means and said adding means are preceded by digital-to-analog converters.