# US 5,349,545 A · Arithmetic logic unit dequantization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,349,545 A - Document ID: US5349545A - Status: Granted - Kind: A - Application number: 07/981,322 - Filed: 1992-11-24 - Granted: 1994-09-20 - Earliest claimed: 1992-11-24 - Assignees: Intel Corporation - Inventors: Michael Keith - Web page: https://patentgrep.com/patent/US5349545A ## CPC - G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} - G06F 7/544: for evaluating functions by calculation {(G06F7/4824 takes precedence)} - H04N 19/126: Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers - H04N 19/124: Quantisation - H04N 19/13: Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC] - H04N 19/60: using transform coding - H04N 19/91: Entropy coding, e.g. variable length coding [VLC] or arithmetic coding - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A device for dequantizing signals is provided in which two hardware operations are generated. The first hardware operation generates a signal representative of a binary function s(a,b) wherein the input signal b is shifted, incremented and decremented to provide signals 2b+1, 2b and 2b-1. A selector selects the first of these signals when a is positive, the second when a is zero, and the third when a is negative. The second signal generated is representative of a unary function t(c). In this function signal c is incremented and decremented to provide signals c-1, c and c+1. A selector selects the first of these signals when c is positive, the second when c is zero, and the third when c is negative. The selected signal in the unary operation is applied to a further selector which also receives signal c as an input. One of the two signals applied to the further selector is selected according to whether signal c is odd or even. Signals s(a,b) and t(c) are then combined by applying the signal s(a,b) to the c input of t(c) to implement the conventional dequantization formula d=Q*(2*v+ sign(v)) if d is even d=d-sign(d). ## Claims ### Claim 1 A device for dequantization of signals, said device having inputs for receiving at least first and second input signals, comprising: a first shifter for shifting said second input signal to provide a third shifter signal; a first addition device for adding a fourth signal to said third shifted signal to provide a first added signal; a second addition device for adding a fifth signal to said third shifted signal to provide a second added signal; and, first selector means for receiving said third shifted signal and said first added signal and said second added signal and for applying a selected one of said third shifted or first added or second added signals to a first selector means output in accordance with said first input signal. ### Claim 2 (depends on 1) The device for dequantization of signals of claim 1, wherein said first addition device adds a signal representative of the value one to provide a first added signal equal to said third shifted signal plus one. ### Claim 3 (depends on 1) The device for dequantization of signals of claim 1, wherein said second addition device adds a signal representative of the value negative one to provide a second added signal equal to said third shifted signal minus one. ### Claim 4 (depends on 1) The device for dequantization of signals of claim 1, wherein said first shifter means comprises means for shifting said first input signal left. ### Claim 5 (depends on 1) The device for dequantization of signals of claim 1, wherein said first selector means further comprises means for selecting in accordance with the magnitude and sign of said first input signal. ### Claim 6 (depends on 5) The device for dequantization of signals of claim 5, wherein said first selector means further comprises: means for selecting said first added signal when said first input signal is positive; means for selecting said third shifted signal when said first input signal is zero; and, means for selecting said second added signal when said first input signal is negative. ### Claim 7 (depends on 1) The device for dequantization of signals of claim 1, wherein said first and second input signals are represented by a and b respectively and the signal of said first selector means output is represented by: ##EQU4## ### Claim 8 (depends on 7) The device for dequantization of signals of claim 7, wherein said first shifter, said first addition device said second addition device and said first selector means are disposed on an integrated circuit processor device. ### Claim 9 (depends on 1) The device for dequantization of signals of claim 1, said device having a third input signal, further comprising: a third addition device for adding a sixth signal to said third input signal to provide a third added signal; a fourth addition device for adding a seventh signal to said third input signal to provide a fourth added signal; second selector means for receiving said third input signal and said third and fourth added signals and applying a selected one of said second received signals to a second selector means output in accordance with the magnitude and sign of said third input signal; and, third selector means for receiving said third input signal and said second selector output signal and applying a selected one of said third received signals to a third selector means output in accordance with whether said third input signal is even or odd. ### Claim 10 (depends on 9) The device for dequantization of signals of claim 9, wherein said third input signal is represented as c and the signal of said second selector means output is represented by: ##EQU5## ### Claim 11 (depends on 9) The device of claim 9, wherein said third input signal is the signal from said first selector means output. ### Claim 12 (depends on 1) The device of claim 1, wherein said first and second input signals are equal.