# US 5,349,353 A · Method and apparatus for mixed analog and digital processing of delta modulated pulse streams including digital-to-analog conversion of a digital input signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,349,353 A - Document ID: US5349353A - Status: Granted - Kind: A - Application number: 07/997,498 - Filed: 1992-12-28 - Granted: 1994-09-20 - Earliest claimed: 1992-12-28 - Inventors: Djuro G. Zrilic - Web page: https://patentgrep.com/patent/US5349353A ## CPC - G06F 7/5235: {using indirect methods, e.g. quarter square method, via logarithmic domain} - G06J 1/00: Hybrid computing arrangements - H03H 7/24: Frequency- independent attenuators - H03M 3/02: Delta modulation, i.e. one-bit differential modulation {(H03M3/30 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06J: HYBRID COMPUTING ARRANGEMENTS (optical hybrid computing devices G06E3/00) - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A digital processing circuit and method includes a signal modulator connected to modulate a delta-modulated first input signal with a digital second input signal to produce a delta modulated output pulse stream. The digital output can be directly used for many purposes, or the digital output can be demodulated to produce an analog output signal using a low pass filter. Also, if desired, the delta modulated pulse first pulse stream can be generated from an analog signal input through use of a sigma-delta modulator. The signal modulator includes a plurality of switches, each operated by a respective bit of the digital second input signal to switch between the delta modulated first input signal and a known pulse sequence, such as an idle sequence, for delivery to a switch output. A plurality of adder circuits are connected in series to add the successive outputs of the plurality of switches to the delta modulated pulse first input signal to produce the delta modulated output pulse stream. Each of the adder circuits comprises a full binary adder and a D-type flip-flop, the full binary adder having two binary signal inputs and a carry input, and having a sum output and a carry output, the sum output being connected to the carry input through the D-type flip-flop. The known pulse sequence, such as the idle sequence is connected to the input of the first adder circuit. The circuit can be used for many purposes, for example, to provide a multiplying digital-to-analog signal converter, a precision attenuator, or the like, without a requirement for precision components, circuit matching or other special analog signal matching techniques. ## Claims ### Claim 1 A digital processing circuit comprising: a source for producing a sigma-delta modulated pulse density stream first input signal; a first node for receiving the sigma-delta modulated pulse density stream first input signal; a second node for receiving a digital second input signal; a source of pulses having a known pulse sequence; a delta adder circuit connected to receive said pulses having a known pulse sequence on a first input, and having a second input; and a switch connected to receive said first input signal and said source of pulses having a known pulse sequence for selectively connecting either the first input signal or said pulses having a known pulse sequence to the second input of said delta adder circuit in accordance with a state of the second input signal to produce a sigma-delta modulated output pulse density stream at an output of said delta adder circuit. ### Claim 2 (depends on 1) The circuit of claim 1 further comprising a low pass filter for demodulating the sigma-delta modulated output pulse density stream to produce an analog output signal. ### Claim 3 (depends on 1) The circuit of claim 1 further comprising an analog input node for receiving an analog input signal, and wherein said source for producing a sigma-delta modulated pulse density stream first input signal comprises a sigma-delta modulator connected to said analog input node to convert said analog input signal to said sigma-delta modulated pulse density stream first input signal for delivery to said first node. ### Claim 4 (depends on 1) The circuit of claim 1 wherein said signal modulator comprises: a plurality of switches, each operated by a respective bit of said digital second input signal to switch between the sigma-delta modulated first input signal and a known pulse sequence for delivery to a switch output; a plurality of adder circuits connected in series to add the successive outputs of said plurality of switches to the sigma-delta modulated pulse first input signal to produce the sigma-delta modulated output pulse density stream. ### Claim 5 (depends on 4) The circuit of claim 4 further comprising a source of idle sequence pulses, said idle sequence pulses providing said known pulse sequence. ### Claim 6 (depends on 4) The circuit of claim 4 in which each of said adder circuits comprises a full binary adder and a D-type flip-flop, said full binary adder having two binary signal inputs and a carry input, and having a sum output and a carry output, said sum output being connected to said carry input through said D-type flip-flop. ### Claim 7 (depends on 6) The circuit of claim 6 wherein a first one of said adder circuits is connected to receive said known pulse sequence. ### Claim 8 (depends on 7) The circuit of claim 7 further comprising a source of idle sequence pulses, said idle sequence pulses providing said known pulse sequence. ### Claim 9 (depends on 2) The circuit of claim 2 wherein said demodulator comprises a low pass filter. ### Claim 10 (depends on 2) The circuit of claim 2 wherein said demodulator is a low pass filter. ### Claim 11 A digital to analog converter for converting a digital signal having a plurality of bits, comprising: a sigma-delta modulator for encoding an analog reference signal to produce a sigma-delta modulated pulse stream reference signal; a delta adder for modulating the sigma-delta modulated pulse stream reference signal with a digital input signal to produce a digital sigma-delta modulated pulse density stream output signal; and a low pass filter for demodulating the digital sigma-delta modulated pulse density stream output signal to produce an analog output signal. ### Claim 12 (depends on 11) The digital to analog converter of claim 11 wherein said delta adder comprises: a plurality of adder circuits connected in series to weight and cumulatively add the sigma-delta modulated pulse stream reference signal in accordance with the logic states of the bits of the digital signal. ### Claim 13 (depends on 12) The circuit of claim 12 in which each of said adder circuits comprises a full binary adder and a D-type flip-flop, said full binary adder having two binary signal inputs and a carry input, and having a sum output and a carry output, said sum output being connected to said carry input through said D-type flip-flop. ### Claim 14 (depends on 13) The circuit of claim 13 wherein a first one of said adder circuits is connected to receive an idle pulse sequence. ### Claim 15 An attenuator circuit for attenuating an input signal in accordance with the state of the bits of a digital control signal, comprising: a sigma-delta modulator for encoding an analog input signal to produce a sigma-delta modulated pulse stream input signal; a delta adder for modulating the sigma-delta modulated pulse stream input signal with the digital control signal to produce a digital sigma-delta modulated pulse density stream output signal; and a low pass filter for demodulating the digital sigma-delta modulated pulse density stream output signal to produce an analog output signal. ### Claim 16 (depends on 15) The digital to analog converter of claim 15 wherein said delta adder comprises: a plurality of adder circuits connected in series to weight and cumulatively add the sigma-delta modulated pulse stream input signal in accordance with the logic states of the bits of the digital control signal. ### Claim 17 (depends on 16) The circuit of claim 16 in which each of said adder circuits comprises a full binary adder and a D-type flip-flop, said full binary adder having two binary signal inputs and a carry input, and having a sum output and a carry output, said sum output being connected to said carry input through said D-type flip-flop. ### Claim 18 (depends on 17) The circuit of claim 17 wherein a first one of said adder circuits is connected to receive an idle pulse sequence. ### Claim 19 A method for digitally multiplying an input signal by a digital signal to produce a multiplied output signal, comprising: providing the input signal in a binary sigma-delta modulated signal form; depending upon the state of each successive bit of the digital signal, selectively adding the binary sigma-delta modulated signal to a weighted, cumulating sum, beginning with an idle sequence to produce a binary sigma-delta modulated pulse density stream signal output. ### Claim 20 (depends on 19) The method of claim 19 further comprising a demodulating the binary sigma-delta modulated pulse density stream signal output to provide an analog output signal. ### Claim 21 (depends on 19) The method of claim 19 wherein said step of selectively adding the binary sigma-delta modulated signal comprises providing a plurality of serially connected adding stages, each comprising a full binary adder and a D-type flip-flop, said full binary adder having two binary signal inputs and a carry input, and having a sum output and a carry output, said sum output being connected to said carry input through said D-type flip-flop. ### Claim 22 (depends on 20) The method of claim 20 wherein said step of demodulating the binary sigma-delta modulated signal output comprises low pass filtering the binary sigma-delta modulated signal output. ### Claim 23 A digital processing circuit comprising: a source for producing a sigma-delta modulated pulse density stream first input signal; a first node for receiving said sigma-delta modulated pulse first input signal; a second node for receiving a digital second input signal; a third node for receiving a digital third input signal; a first signal modulator connected to receive said first and second input signals and for modulating the first input signal with the second input signal to produce an intermediate sigma-delta modulated output pulse density stream; and a second signal modulator connected to receive said intermediate sigma-delta modulated output pulse density stream and third input signals and for modulating said intermediate signal with said third input signal to produce an output sigma-delta modulated output pulse density stream. ### Claim 24 (depends on 23) The circuit of claim 23 further comprising a low pass filter for demodulating the output sigma-delta modulated output pulse density stream to produce an analog output signal. ### Claim 25 (depends on 23) The circuit of claim 23 further comprising an analog input node for receiving an analog input signal, and a sigma-delta modulator connected to said analog input node to convert said analog input signal to said sigma-delta modulated pulse first input signal for delivery to said first node. ### Claim 26 (depends on 23) The circuit of claim 23 wherein said first and second signal modulators each comprises: a plurality of switches, each operated by a respective bit of a digital input signal to switch between a sigma-delta modulated input signal and a known pulse sequence for delivery to a switch output; a plurality of adder circuits connected in series to add the successive outputs of said plurality of switches to the sigma-delta modulated pulse input signal to produce a sigma-delta modulated output pulse density stream. ### Claim 27 (depends on 26) The circuit of claim 26 further comprising a source of idle sequence pulses, said idle sequence pulses providing said known pulse sequence. ### Claim 28 (depends on 26) The circuit of claim 26 in which each of said adder circuits comprises a full binary adder and a D-type flip-flop, said full binary adder having two binary signal inputs and a carry input, and having a sum output and a carry output, said sum output being connected to said carry input through said D-type flip-flop. ### Claim 29 (depends on 28) The circuit of claim 28 wherein a first one of said adder circuits is connected to receive said known pulse sequence. ### Claim 30 (depends on 29) The circuit of claim 29 further comprising a source of idle sequence pulses, said idle sequence pulses providing said known pulse sequence. ### Claim 31 (depends on 24) The circuit of claim 24 wherein said demodulator comprises a low pass filter. ### Claim 32 (depends on 24) The circuit of claim 24 wherein said demodulator is a low pass filter. ### Claim 33 (depends on 23) The circuit of claim 23 wherein said second and third signals are digital signals of different width. ### Claim 34 (depends on 23) The circuit of claim 23 wherein said second and third signals are digital signals of the same width. ### Claim 35 A digital processing circuit for converting a digital input signal having a plurality of weighted bits into a pulse density serial signal, comprising: a source for producing a sigma-delta modulated pulse density stream first input signal; a plurality of switches operated to select between a first and a second pole in accordance with a state of a respective weighted bit of said digital input signal; said first pole being connected to receive the sigma-delta modulated pulse density first input signal; said second pole being connected to receive a delta idle sequence second input signal; a plurality of delta adder circuits, each associated with a respective weighted bit of said digital input signal, said adder circuits being connected in series to add the successive outputs of said plurality of switches to the delta modulated second input signal to produce a sigma-delta modulated output pulse density stream; and a signal modulator connected to receive said first and second input signals and for modulating the first input signal with the second input signal to produce the sigma-delta modulated output pulse density stream. ### Claim 36 (depends on 35) A digital processing circuit of claim 35 further comprising a low pass filter demodulator connected to receive the output sigma-delta pulse density stream to produce an analog output signal.