# US 5,349,352 A · Analog-to-digital converter having high AC line noise rejection and insensitive to AC line frequency variations

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- Number: US 5,349,352 A
- Document ID: US5349352A
- Status: Granted
- Kind: A
- Application number: 07/994,008
- Filed: 1992-12-21
- Granted: 1994-09-20
- Earliest claimed: 1992-12-21
- Assignees: Harris Corporation
- Inventors: Farid Saleh
- Web page: https://patentgrep.com/patent/US5349352A

## CPC

- H03M 1/0624: {by synchronisation}
- H03M 3/324: {characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement}
- H03M 3/458: {Analogue/digital converters using delta-sigma modulation as an intermediate step}
- H03M 1/0845: {of power supply variations, e.g. ripple}
- H03M 1/52: Input signal integrated with linear return to datum
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Analog-to-digital (AID) converters with power line frequency noise rejection by synchronization of the converter clock with the power line frequency through a phase locked loop. Both sigma delta and integrating A/D converters may use the synchronized clock to precisely reject power line frequency noise.

## Claims

### Claim 1

An analog-to-digital converter, comprising:
(a) a sigma-delta modulator;
(b) a digital filter coupled to said modulator;
(c) a clock generator providing clock signals at a clock frequency to said modulator and to said filter, wherein said clock frequency is a fixed multiple of a variable power line frequency; and
(d) wherein said digital filter is a comb filter with a notch at a fixed fraction of said clock frequency which equals said power line frequency.

### Claim 2 (depends on 1)

The converter of claim 1, wherein:
(a) said power line frequency is centered at 60 Hz.

### Claim 3 (depends on 1)

The converter of claim 1, wherein:
(a) said power line frequency is centered at 50 Hz.

### Claim 4 (depends on 1)

The converter of claim 1, wherein:
(a) said clock generator includes a phase-loop coupled to a power line at said power line frequency.

### Claim 5

An analog-to-digital converter, comprising:
(a) a sigma-delta modulator;
(b) a digital filter coupled to said modulator;
(c) a clock generator providing clock signals at a clock frequency f.sub.CLK to said modulator and to said filter, said clock generator includes a phase-locked-loop coupled to an AC power line at a frequency f.sub.LINE which may vary but fixes f.sub.CLK =Kf.sub.LINE for a positive integer K; and
(d) wherein said digital filter has a stopband at f.sub.LINE.

### Claim 6 (depends on 5)

The converter of claim 5, wherein:
(a) said filter includes a first filter coupled to a second filter, said first filter decimating the sampling rate of said modulator down to a frequency Mf.sub.LINE with M a positive integer, and said second filter having a stopband at f.sub.LINE.

### Claim 7 (depends on 6)

The converter of claim 6, wherein:
(a) said second filter is an averaging filter which averages M samples.

### Claim 8 (depends on 7)

The converter of claim 7, wherein:
(a) M equals 4.

### Claim 9 (depends on 7)

The converter of claim 7, wherein:
(a) said first filter is a comb filter with a first notch greater than f.sub.LINE.

### Claim 10

An integrating analog-to-digital converter (dual/multislope), comprising:
(a) a signal integrator driven by a clock generator;
(b) said clock generator providing clock signals at a clock frequency f.sub.CLK coupled to said signal integrator, said clock generator including a phase-locked-loop coupled to an AC power line operating at frequency f.sub.LINE which may vary but fixes f.sub.CLK =Kf.sub.LINE for a positive integer K;
(c) wherein the duration of an integrating interval by said signal integrator is an integer multiple of 1/f.sub.LINE ; and
(d) wherein the clock frequency of the analog-to-digital converter is continuously adapted to the AC power line frequency.

### Claim 11

An analog-to-digital converter comprising:
(a) a sigma-delta modulator;
(b) a digital filter coupled to said modulator;
(c) a clock generator providing clock signals at a clock frequency to said modulator and to said filter, wherein said clock frequency is a fixed multiple of a variable power line frequency; and
wherein said digital filter includes:
(i) a low pass filter with a cutoff frequency higher than said lower line frequency; and
(ii) an averaging filter coupled to an output of said low pass filter, said averaging filter averaging a fixed integral number of samples for a period of said power line frequency.

### Claim 12 (depends on 11)

The converter of claim 11, wherein:
(a) said clock generator includes a phase-locked-loop coupled to a power line at said power line frequency.

### Claim 13 (depends on 11)

The converter of claim 11, wherein:
(a) said power line frequency is centered at 60 Hz.

### Claim 14 (depends on 11)

The converter of claim 11, wherein:
(a) said power line frequency is centered at 50 Hz.

### Claim 15

An analog-to-digital converter comprising:
(a) a sigma-delta modulator;
(b) a digital filter coupled to said modulator;
(c) a clock generator providing clock signals at a clock frequency f.sub.CLK to said modulator and to said filter, said clock generator includes a phase-locked-loop coupled to an AC power line at a frequency f.sub.LINE which may vary but fixes f.sub.CLK =Kf.sub.LINE for a positive integer K; and
(d) wherein said digital filter is an Nth order comb filter with a notch at f.sub.LINE.

### Claim 16 (depends on 15)

The converter of claim 15, wherein:
(a) said notch is the nth notch for a positive integer n.