# US 5,349,243 A · Latch controlled output driver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,349,243 A - Document ID: US5349243A - Status: Granted - Kind: A - Application number: 08/085,760 - Filed: 1993-06-30 - Granted: 1994-09-20 - Earliest claimed: 1993-06-30 - Assignees: SGS-Thomson Microelectronics S.A. - Inventors: David C. McClure - Web page: https://patentgrep.com/patent/US5349243A ## CPC - H03K 19/0013: {in field effect transistor circuits} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An output driver includes a pull-up and a pull-down transistor in series between an upper and a lower power supply voltage. Each transistor is controlled by a latch connected to its gate. Control transistors are cross-coupled between inputs to the latches and a power supply voltage to force at least one of the latches to be in a known state. This prevents both of the transistors from turning on simultaneously. ## Claims ### Claim 1 A latch controlled output driver circuit comprising: an output driver circuit including a pull-up transistor and a pull-down transistor, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage; a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor; a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor; a first gate having an output connected to the input of the first latch circuit; a second gate having an output connected to the input of the second latch circuit; a first control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit; and a second control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit. ### Claim 2 (depends on 1) The latch controlled output driver circuit of claim 1, wherein the first gate has an input connected to a true data line and the second gate has an input connected to a complement data line. ### Claim 3 (depends on 2) The latch controlled output driver circuit of claim 2, wherein the first and second control transistors are p-channel MOSFETs. ### Claim 4 (depends on 3) The latch controlled output driver circuit of claim 3, wherein the pull-up transistor and the pull-down transistor are n-channel MOSFETs. ### Claim 5 (depends on 1) The latch controlled output driver circuit of claim 1, wherein the gates are controlled by a clock signal. ### Claim 6 (depends on 1) The latch controlled output driver circuit of claim 1, wherein the first latch circuit includes a first inverter and a second inverter, the input of the first latch circuit being connected to an input of the first inverter and an output of the second inverter and the output of the first latch circuit being connected to the output of the first inverter and the input of the second inverter and wherein the second latch circuit includes a third inverter and a fourth inverter, the input of the second latch circuit being connected to the input of the third inverter and the output of the fourth inverter and the output of the second latch circuit being connected to the output of the third inverter and the input of the fourth inverter. ### Claim 7 (depends on 1) The latch controlled output driver circuit of claim 1, wherein the first latch circuit comprises a first inverter, second inverter, a third inverter, and a fourth inverter connected in series, wherein the input of the first latch circuit is connected to an input of the first inverter and an output of the fourth inverter and the output of the first latch circuit being connected to an output of the second inverter and an input of the third inverter. ### Claim 8 (depends on 1) The latch controlled output driver circuit of claim 1, wherein the first and second gates are pass gates. ### Claim 9 A memory comprising: a plurality of memory groups having a plurality of outputs; and a data bus circuit having a plurality of inputs connected the plurality of outputs, the data bus circuit having a latch controlled output driver circuit that includes: an output driver circuit including a pull-up transistor and a pull-down transistor, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage; a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor; a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor; a first gate having an output connected to the input of the first latch circuit; a second gate having an output connected to the input of the second latch circuit; a first control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit; and a second control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit. ### Claim 10 (depends on 9) The memory of claim 9, wherein the first gate has an input connected to a true data line and the second gate has an input connected to a complement data line. ### Claim 11 (depends on 10) The memory of claim 10, wherein the first and second control transistors are p-channel MOSFETs. ### Claim 12 (depends on 11) The memory of claim 11, wherein the pull-up transistor and the pull-down transistor are n-channel MOSFETs. ### Claim 13 (depends on 12) The memory of claim 12, wherein the gates are controlled by a clock signal. ### Claim 14 (depends on 12) The memory of claim 12, wherein the first latch circuit includes a first inverter and a second inverter, the input of the first latch circuit being connected to an input of the first inverter and an output of the second inverter and the output of the first latch circuit being connected to the output of the first inverter and the input of the second inverter and wherein the second latch circuit includes a third inverter and a fourth inverter, the input of the second latch circuit being connected to the input of the third inverter and the output of the fourth inverter and the output of the second latch circuit being connected to the output of the third inverter and the input of the fourth inverter. ### Claim 15 (depends on 12) The memory of claim 12, wherein the first latch circuit comprises a first inverter, second inverter, a third inverter, and a fourth inverter connected in series, wherein the input of the first latch circuit is connected to an input of the first inverter and an output of the fourth inverter and the output of the first latch circuit being connected to an output of the second inverter and an input of the third inverter. ### Claim 16 (depends on 9) The memory of claim 9, wherein the first and second gates are pass gates. ### Claim 17 A control circuit for controlling first and second output transistors in a driver circuit comprising: first and second latches, each latch having an output and an input, the first latch having an output connected to a gate of the first output transistor, and the second latch having an output connected to a gate of the second output transistor; first and second gates, each gate having an output and an input, the output of the first gate being connected to the input of the first latch and the output of the second gate being connected to the input of the second latch; and a regulation circuit connected to the latch inputs for preventing both inputs from simultaneously having a selected state, wherein the selected state at a latch inputs causes a corresponding output transistor to be turned on. ### Claim 18 (depends on 17) The control circuit of claim 17, wherein the regulation circuit comprises: a first regulation transistor having a source connected to an upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit; and a second regulation transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit. ### Claim 19 (depends on 18) The control circuit of claim 18, wherein the first and second regulation transistors are p-channel transistors. ### Claim 20 (depends on 19) The control circuit of claim 19, wherein the sources of the first and second regulation transistors are connected to a positive upper power supply voltage. ### Claim 21 (depends on 17) The control circuit of claim 17, wherein the first and second gates are pass gates.