Field effect transistor with a lightly doped drain

A method of forming a transistor device comprising the steps of:

• providing a semiconductor layer including a top surface;
• forming a first source/drain region of a first conductivity type in said semiconductor layer;
• forming a second source/drain region of said first conductivity the in said semiconductor layer spaced from said first source/drain region by a channel region, said second source/drain region comprising:
• a lightly doped portion of said first conductivity type adjacent said channel region and abutting said top surface, said lightly doped portion having a first doping concentration;
• a main portion of said first conductivity type abutting said top surface and spaced from said channel region by said lightly doped portion said main portion having a second doping concentration which is greater than said first doping concentration;
• a deep portion of said first conductivity the formed within said layer and spaced from said top surface by said lightly doped portion and said main portion said deep portion having a third doping concentration which is greater than said first doping concentration but less than said second doping concentration;
• and
• forming a gate electrode over at least a portion of said channel region and insulated therefrom.

A method of forming a transistor including a lightly doped drain comprising the steps of:

• providing a semiconductor layer including a top surface;
• forming a gate dielectric layer over a portion of said top surface;
• forming a gate electrode over at least a portion of said gate dielectric layer, said gate electrode including first and second edges;
• implanting dopants of a first conductivity type to form a first deep source/drain region in said semiconductor layer and aligned to said first edge of said gate electrode, said first deep source/drain region spaced from said top surface;
• forming a first sidewall insulating region adjacent said first edge of said gate electrode and a second sidewall insulating region adjacent said second edge of said gate electrode;
• and
• forming a first main source/drain region in said semiconductor layer abutting said top surface and aligned to said first sidewall insulating region and forming a second main source/drain region in said semiconductor layer abutting said top surface and aligned to said second sidewall insulating region said first and second main source/drain regions being doped with dopants of said first conductivity type.

A method of forming a transistor device comprising the steps of:

• providing a semiconductor layer including a top surface;
• forming a deep portion of a first source/drain region within said semiconductor layer and spaced from said top surface, said deep portion being doped with dopants of a first conductivity type, and said deep portion having a first doping concentration;
• forming a lightly doped portion of said first source/drain region within said semiconductor layer and abutting a portion of said top surface and adjacent said channel region, said lightly doped portion being doped with dopants of said first conductivity type and having a second doping concentration which is less than said first doping concentration;
• forming a main portion of said first source/drain region within said semiconductor layer, said main portion abutting said top surface and adjacent said lightly doped portion, said main portion disposed above said deep portion, said main portion being doped with dopants of said first conductivity type and having a third doping concentration which is less than said first doping concentration and greater than said second doping concentration;
• forming a second source/drain region within said semiconductor layer and spaced from said lightly doped portion of said first source/drain region by a channel region, said second source/drain region being doped with dopants of said first conductivity type;
• and
• forming a gate electrode over at least a portion of said channel region and insulated therefrom.