# US 5,349,224 A · Integrable MOS and IGBT devices having trench gate structure

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- Number: US 5,349,224 A
- Document ID: US5349224A
- Status: Granted
- Kind: A
- Application number: 08/085,845
- Filed: 1993-06-30
- Granted: 1994-09-20
- Earliest claimed: 1993-06-30
- Assignees: Purdue Research Foundation
- Inventors: Percy V. Gilbert; Gerold W. Neudeck
- Web page: https://patentgrep.com/patent/US5349224A

## CPC

- H10D 30/658: {having trench gate electrodes}
- H10D 12/01: Manufacture or treatment
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 12/491: {having both emitter contacts and collector contacts in the same substrate side}
- H10D 64/0133: {at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/511: {for IGFETs}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A power semiconductor device which is integrable in an integrated circuit includes a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween, second and third doped regions of a second conductivity type formed in the first doped region, the second and third doped regions being spaced apart and abutting the first surface, and fourth and fifth doped regions of the first conductivity type respectively formed in the second and third doped regions and abutting the first surface. Sixth and seventh doped regions extend from the first surface into the first region, the sixth region being adjacent to the second and fourth regions and spaced therefrom by an electrically insulative layer, the seventh region being adjacent to the third and fifth regions and spaced therefrom by an insulative layer. The first doped region extends toward the first surface between the sixth and seventh regions and separated therefrom by an electrically insulative layer of variable thickness suitable for voltage blocking. An eighth doped region in the first doped region between the sixth and seventh regions abuts the first surface and forms the drain of a MOSFET or the anode of an IGBT. In fabricating the device, reactive ion etching is used to from a trench in which the sixth and seventh regions are formed. The trench is filled by epitaxially grown semiconductor material in which the eighth doped region is formed. The fourth and fifth doped regions form the source of a MOSFET or a cathode of an IGBT. All ohmic contacts to the device can be made on the first surface.

## Claims

### Claim 1

A power semiconductor device which is integrable in an integrated circuit comprising
a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,
second and third doped regions of a second conductivity type formed in said first doped region, said second and third doped regions being spaced apart and abutting said first surface,
fourth and fifth doped regions of said first conductivity type respectively formed in said second and third doped regions and abutting said first surface,
sixth and seventh doped regions extending from said first surface into said first region, said sixth region being adjacent to said second and fourth regions and spaced therefrom by an electrically insulative gate layer, said seventh region being adjacent to said third and fifth regions and spaced therefrom by an electrically insulative gate layer,
said first doped region extending toward said first surface between said sixth and seventh regions and separated from said sixth and seventh regions by an electrically insulative layer of suitable thickness for voltage blocking, and
an eighth doped region in said first doped region between said sixth and seventh regions and abutting said first surface.

### Claim 2 (depends on 1)

The power semiconductor device as defined by claim 1 and further including
an ohmic contact to said second and fourth regions,
an ohmic contact to said third and fifth regions, and
an ohmic contact to said sixth and seventh regions.

### Claim 3 (depends on 1)

The power semiconductor device as defined by claim 1 wherein said eighth doped region is of said first conductivity type, said device being a power MOSFET.

### Claim 4 (depends on 3)

The power semiconductor device as defined by claim 3 wherein said first conductivity type is N type and said second conductivity type is P type.

### Claim 5 (depends on 1)

The power semiconductor device as defined by claim 1 wherein said sixth and seventh doped regions are of first conductivity type.

### Claim 6 (depends on 1)

The power semiconductor device as defined by claim 1 wherein said eighth doped region is of second conductivity type, said device being an IGBT.

### Claim 7 (depends on 6)

The power semiconductor device as defined by claim 6 wherein said first conductivity type is N type and said second conductivity type is P type.

### Claim 8 (depends on 7)

The power semiconductor device as defined by claim 7 wherein said sixth and seventh regions are of first conductivity type.

### Claim 9

A power MOSFET device comprising
a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,
first and second double diffused regions formed in said first doped region, said first and second double diffused regions being spaced apart and abutting said first surface,
first and second gate electrodes extending from said first surface into said first doped region, said first gate electrode being adjacent to said first double diffused region and spaced therefrom by an electrically insulative layer, said second gate electrode layer being adjacent to said second double diffused region and spaced therefrom by an electrically insulative layer,
said first region extending to said first surface between said first and second gate electrodes and separated therefrom by an electrically insulative layer of suitable thickness for voltage blocking, and
a drain region of said first conductivity type in said first doped region between said gate electrodes and abutting said first surface,
said first and second double diffused regions comprising source and channel regions of said device.

### Claim 10 (depends on 9)

The power MOSFET device as defined by claim 9 wherein said drain region has a higher dopant concentration than said first region.

### Claim 11 (depends on 10)

The power MOSFET device as defined by claim 10 and further including an ohmic contact to said source regions, an ohmic contact to said drain regions, and an ohmic contact to said gate electrodes.

### Claim 12 (depends on 11)

The power MOSFET device as defined by claim 11 wherein said first conductivity type is N type and said second conductivity type is P type.

### Claim 13

An insulated gate bipolar transistor (IGBT) device comprising
a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,
first and second double diffused regions formed in said first doped region, said first and second double diffused regions being spaced apart and abutting said first surface,
first and second gate electrodes extending from said first region into said first doped region, said first gate electrode being adjacent to said first double diffused region and spaced therefrom by an electrically insulative layer, said second gate electrode being adjacent to said second double diffused region and spaced therefrom by an electrically insulative layer,
said first region extending towards said first surface between said first and second gate electrodes and separated from said first and second gate electrodes by an electrically insulative layer of suitable thickness for voltage blocking, and
a doped region of a second conductivity type in said first doped region between said first and second gate electrodes and functioning as an anode, said first and second double diffused regions functioning as cathodes and channel regions of said device.

### Claim 14 (depends on 10)

The IGBT device as defined by claim 10 and further including an ohmic contact to said anode, an ohmic contact to said cathode, and an ohmic contact to said gate.

### Claim 15 (depends on 14)

The IGBT device as defined by claim 14 wherein said first conductivity type is N type and said second conductivity type is P type.

### Claim 16

A method of fabricating a power semiconductor device which is integrable in an integrated circuit comprising the steps of
a) providing a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,
b) forming a first surface region in said first doped region with dopant of a second conductivity type, said surface region abutting said first surface,
c) forming a second surface region of said first conductivity type in said first surface region, said second surface region abutting said first surface,
d) forming a trench through said first surface region, said second surface region, and into said first doped region, said trench having exposed sidewalls and a bottom surface,
e) forming electrically insulative layers on said sidewalls,
f) forming conductive layers over said electrically insulative layers on said sidewalls,
g) forming electrically insulative layers of suitable thickness for voltage blocking on said conductive layers,
h) filling said trench with semiconductor material selectively epitaxially grown said bottom surface, and
i) doping a surface portion of said semiconductor material in said trench.

### Claim 17 (depends on 16)

The method as defined by claim 16 wherein said conductive layers comprise doped polysilicon.

### Claim 18 (depends on 17)

The method as defined by claim 17 and further including
forming contacts to said first and second surface regions,
forming contacts to said surface portion of said semiconductor material between said doped polysilicon layers, and
forming a contact to said doped polysilicon layers.

### Claim 19 (depends on 16)

The method as defined by claim 16 wherein step i) includes doping a surface portion of said semiconductor material in said trench with dopant of said first conductivity type, said device being a MOSFET.

### Claim 20 (depends on 16)

The method as defined by claim 16 wherein step i) includes doping a surface portion of said semiconductor material in said trench with dopant of said second conductivity type, said device being an IGBT.

### Claim 21 (depends on 16)

The method as defined by claim 16 and further including after step b) the step of doping a portion of said first surface region with dopant of said second conductivity type to increase the dopant concentration.

### Claim 22 (depends on 16)

The method as defined by claim 16 wherein step d) includes reactive ion etching.

### Claim 23 (depends on 22)

The method as defined by claim 22 wherein steps e) and g) form thermally grown silicon oxide of variable thickness.

### Claim 24

A microelectronic gated device comprising
a monocrystalline semiconductor substrate having a trench therein at one face thereof, said trench including a trench sidewall;
a relatively thin first insulating layer on said trench sidewall for gate oxide;
a gate electrode on said relatively thin first insulating layer;
a relatively thick second insulating layer on said gate electrode for voltage blocking;
a monocrystalline semiconductor region on said relatively thick second insulating layer, and extending from said substrate to said one face;
first contact means for electrically contacting said monocrystalline semiconductor region at said one face; and
second contact means for electrically contacting said monocrystalline semiconductor substrate at said one face.