# US 5,349,214 A · Complementary heterojunction device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,349,214 A - Document ID: US5349214A - Status: Granted - Kind: A - Application number: 08/119,554 - Filed: 1993-09-13 - Granted: 1994-09-20 - Earliest claimed: 1993-09-13 - Assignees: Motorola, Inc. - Inventors: Saied N. Tehrani; X. Theodore Zhu; Herbert Goronkin; Jun Shen - Web page: https://patentgrep.com/patent/US5349214A ## CPC - H10D 84/01: Manufacture or treatment - H10D 84/85: Complementary IGFETs, e.g. CMOS - Y10S 148/015: Capping layer - Y10S 148/072: Heterojunctions - Y10S 148/16: Superlattice - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ## Abstract A heterojunction device including a first semiconductive layer on a substrate, a barrier layer on the first layer, a second semiconductive layer on the barrier layer and a multi-layer cap, on the second semiconductive layer. First and second gates positioned on layers of the cap to define first and second transistors, with the cap layers being selected and etched to pin the Fermi level in a first transistor conduction channel in the second semiconductive layer such that the number of carriers in the first conduction channel are substantially less than the number of carriers in surrounding portions of the second semiconductive layer and the Fermi level in a second transistor conduction channel in the first semiconductive layer such that the number of carriers in the second conduction channel are substantially less than the number of carriers in surrounding portions of the first semiconductive layer. ## Claims ### Claim 1 A heterojunction device comprising: a supporting substrate structure defining a supporting surface; a first semiconductive layer of material having a conduction band and a valence band, each with a predetermined energy level, and with a Fermi level, the first semiconductive layer being positioned on the supporting surface of the substrate structure; a first barrier layer positioned on the first semiconductive layer; a second semiconductive layer of material having a conduction band and a valence band, each with a predetermined energy level, and with a Fermi level, the second semiconductive layer being positioned on the first barrier layer; a cap structure positioned on the second semiconductive layer and including a plurality of layers of selected semiconductor materials; and a first transistor having a conduction channel in the second semiconductive layer and a second transistor having a conduction channel in the first semiconductive layer, each of the first and second transistors including gate, source and drain electrodes, the cap structure being selected and etched to pin the Fermi level in the conduction channel of the first transistor such that carriers in the conduction channel of the first transistor are substantially less than carriers in surrounding portions of the second semiconductive layer and to pin the Fermi level in the conduction channel of the second transistor such that carriers in the conduction channel of the second transistor are substantially less than carriers in surrounding portions of the first semiconductive layer. ### Claim 2 (depends on 1) A heterojunction device as claimed in claim 1 wherein the supporting substrate structure includes a buffer layer formed on a surface of a substrate. ### Claim 3 (depends on 2) A heterojunction device as claimed in claim 2 wherein the supporting substrate structure further includes a barrier layer formed on a surface of the buffer layer. ### Claim 4 (depends on 1) A heterojunction device as claimed in claim 1 wherein the cap structure includes a first barrier layer positioned on the second semiconductive layer of material. ### Claim 5 (depends on 1) A heterojunction device as claimed in claim 1 wherein the supporting substrate structure includes a substrate formed of a material selected from the group GaAs, InP and GaSb. ### Claim 6 (depends on 5) A heterojunction device as claimed in claim 5 wherein the supporting substrate structure includes a buffer layer positioned on the substrate and formed of AlSb/GaSb. ### Claim 7 (depends on 6) A heterojunction device as claimed in claim 6 wherein the supporting substrate structure includes a barrier layer positioned on the buffer layer and formed of one of AlSb and AlGaSb. ### Claim 8 (depends on 7) A heterojunction device as claimed in claim 7 wherein the first semiconductive layer includes GaSb, the first barrier layer is formed of one of AlSb and AlGaSb, and the second semiconductive layer includes InAs. ### Claim 9 (depends on 8) A heterojunction device as claimed in claim 8 wherein the cap structure includes a barrier layer positioned on the second semiconductive layer and formed of one of AlSb and AlGaSb. ### Claim 10 (depends on 9) A heterojunction device as claimed in claim 9 wherein the cap structure includes a layer of GaSb positioned on the barrier layer of the cap structure. ### Claim 11 (depends on 10) A heterojunction device as claimed in claim 10 wherein the cap structure includes a layer of InAs positioned on the layer of GaSb of the cap structure. ### Claim 12 (depends on 11) A heterojunction device as claimed in claim 11 wherein the gate of the first transistor is positioned on the layer of InAs included in the cap structure and the source and drain electrodes are positioned on the layer of GaSb included in the cap structure and further positioned on either side of the gate electrode. ### Claim 13 (depends on 12) A heterojunction device as claimed in claim 12 wherein the gate of the second transistor is positioned on the layer of GaSb included in the cap structure and the source and drain electrodes are positioned on the second semiconductive layer including InAs and further positioned on either side of the gate electrode. ### Claim 14 A complimentary heterojunction device comprising: a supporting substrate structure defining a supporting surface; a first semiconductive layer of material of a first type of conductivity having a conduction band and a valence band, each with a predetermined energy level, and with a Fermi level, the first semiconductive layer being positioned on the supporting surface of the substrate structure; a first barrier layer positioned on the first semiconductive layer; a second semiconductive layer of material of a second type of conductivity opposite to the first type, the second semiconductive layer having a conduction band and a valence band, each with a predetermined energy level, and with a Fermi level, the second semiconductive layer being positioned on the first barrier layer; a cap structure positioned on the second semiconductive layer and including a barrier layer, a first cap layer and a second cap layer of different selected semiconductor materials; a first transistor defining a first conduction channel in the second semiconductive layer, the first transistor further including a first gate terminal positioned on the second cap layer of the cap structure in overlying relationship to the first conduction channel and first source and first drain electrodes positioned on the first cap layer and further positioned on either side of the first gate electrode; a second transistor spaced from the first transistor and defining a second conduction channel in the first semiconductive layer, the second transistor further including a second gate terminal positioned on the first cap layer of the cap structure in overlying relationship to the second conduction channel and second source and second drain electrodes positioned on the second semiconductive layer and further positioned on either side of the second gate electrode; and the barrier layer, the first cap layer and the second cap layer of the cap structure being selected to pin the Fermi level in the conduction channel of the first transistor such that carriers in the conduction channel of the first transistor are substantially less than carriers in surrounding portions of the second semiconductive layer and the first cap layer of the cap structure being selected to pin the Fermi level in the conduction channel of the second transistor such that carriers in the conduction channel of the second transistor are substantially less than carriers in surrounding portions of the first semiconductive layer. ### Claim 15 (depends on 14) A complimentary heterojunction device as claimed in claim 14 wherein the cap structure includes material selected to pin the Fermi level in the second semiconductive layer such that the number of carriers in the second semiconductive layer are substantially greater than the number of carriers in the first conduction channel of the second semiconductive layer to provide low resistance access regions between the first drain and source electrodes and the first conduction channel. ### Claim 16 (depends on 14) A complimentary heterojunction device as claimed in claim 14 wherein the cap structure includes material selected to pin the Fermi level in the first semiconductive layer such that the number of carriers in the first semiconductive layer are substantially greater than the number of carriers in the second conduction channel of the first semiconductive layer to provide low resistance access regions between the second drain and source electrodes and the second conduction channel.