# US 5,349,206 A · Integrated memory circuit with high density load elements

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- Number: US 5,349,206 A
- Document ID: US5349206A
- Status: Granted
- Kind: A
- Application number: 07/871,871
- Filed: 1992-04-20
- Granted: 1994-09-20
- Earliest claimed: 1988-11-10
- Assignees: Seiko Epson Corporation
- Inventors: Masakazu Kimura
- Web page: https://patentgrep.com/patent/US5349206A

## CPC

- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10B 10/15: {comprising a resistor load element}
- Y10S 257/903: FET configuration adapted for use as static memory cell
- Y10S 257/904: with passive components,, e.g. polysilicon resistors
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

An integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits. The design further provides for improved mask alignment accuracy since the load element is completely constructed within a planar extent of the memory cell so that predetermined lengths of the element and predetermined, desired resistance levels can be achieved and maintained without concern for resistance level changes due to subsequent integrated circuit processing and contaminate migration.

## Claims

### Claim 1

An integrated circuit comprising a plurality of circuit cells each having load elements and transistors formed relative to a semiconductor substrate, said transistors having source/drain domains with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said cells comprising an insulating layer formed on said substrate, a first conductive layer formed on said insulating layer and electrically connected at a first region to at least one of said domains, said first conductive layer extending laterally away from said first region in a first direction to a second region in proximity to an edge of said circuit cell laterally spaced from said first region, a second conductive layer spatially insulated from and substantially parallel with said first conductive layer and connected to said first conductive layer at an interconnect formed at said second region between said first and second conductive layers, said second conductive layer having a planar extent extending substantially across said cell in a second direction opposite to said first direction, each of said load elements formed in said second conductive layer in a region along said planar extent spaced in said second direction from said interconnect so that said load elements are shielded from contamination by impurity migration from said one domain along said first conductive layer, said planar extent of said second conductive layer increased due to the extension of said first conductive layer to said cell edge permitting an extended length of said load elements to include a correspondingly extended resistance level reducing operational current consumption of said cell while increasing the length of said load connection path to make allowance for said impurity migration, each of said load elements comprises a TFT having a TFT channel formed in said second conductive layer having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 wherein said TFT includes a gate formed both below and above said TFT channel.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 wherein said TFT channel comprises a n.sup.- region.

### Claim 4

An integrated circuit comprising a plurality of circuit cells each having load elements and transistors formed relative to a semiconductor substrate, said transistors having source/drain domains with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said cells comprising an insulating layer formed on said substrate, a first conductive layer formed on said insulating layer and electrically connected at a first region to at least one of said domains, said first conductive layer extending laterally away from said first region in a first direction to a second region in proximity to an edge of said circuit cell laterally spaced from said first region, a second conductive layer spatially insulated from and substantially parallel with said first conductive layer and connected to said first conductive layer at an interconnect formed at said second region between said first and second conductive layers, said second conductive layer having a planar extent extending substantially across said cell in a second direction opposite to said first direction, each of said load elements formed in said second conductive layer in a region along said planar extent spaced in said second direction from said interconnect so that said load elements are shielded from contamination by impurity migration from said one domain along said first conductive layer, said planar extent of said second conductive layer increased due to the extension of said first conductive layer to said cell edge permitting an extended length of said load elements to include a correspondingly extended resistance level reducing operational current consumption of said cell while increasing the length of said load connection path to make allowance for said impurity migration, each of said load elements comprise a resistance formed in said second conductive layer having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 5 (depends on 4)

The integrated circuit of claim 4 wherein said resistance comprises a p.sup.+ region.

### Claim 6

An integrated circuit comprising a plurality of circuit cells each having load elements and transistors formed relative to a semiconductor substrate, said transistors having source/drain domains with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said cells comprising an insulating layer formed on said substrate, a first conductive layer formed on said insulating layer and electrically connected at a first region to at least one of said domains, said first conductive layer extending laterally away from said first region in a first direction to a second region in proximity to an edge of said circuit cell laterally spaced from said first region, a second conductive layer spatially insulated from and substantially parallel with said first conductive layer and connected to said first conductive layer at an interconnect formed at said second region between said first and second conductive layers, said second conductive layer having a planar extent extending substantially across said cell in a second direction opposite to said first direction, each of said load elements formed in said second conductive layer in a region along said planar extent spaced in said second direction from said interconnect so that said load elements are shielded from contamination by impurity migration from said one domain along said first conductive layer, said planar extent of said second conductive layer increased due to the extension of said first conductive layer to said cell edge permitting an extended length of said load elements to include a correspondingly extended resistance level reducing operational current consumption of said cell while increasing the length of said load connection path to make allowance for said impurity migration, said each of said circuit cells comprises a memory cell in a TFT load type static RAM, each of said load elements comprising a TFT channel having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 7

An integrated memory circuit comprising a plurality of circuit cells each having load elements and MOSFETs formed relative to a semiconductor substrate, said MOSFETs having source/drain domains formed in said substrate with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said memory cells comprising an insulating layer formed on said substrate, a first conductive layer formed on said insulating layer and electrically connected at a first region to at least one of said domains, said first conductive layer extending laterally away from said first region in a first direction to a second region in proximity to an edge of said memory cell laterally spaced from said first region, a second conductive layer spatially insulated from and substantially parallel with said first conductive layer and connected to said first conductive layer at an interconnect formed at said second region between said first and second conductive layers, said second conductive layer having a planar extent extending substantially across said memory cell in a second direction opposite to said first direction, each of said load elements formed in said second conductive layer in a region along said planar extent and extending in said second direction from said interconnect so that said load elements are not present in said second region of said interconnect, said planar extent of said second conductive layer increased due to the extension of said first conductive layer to said cell edge permitting an extended length of said load elements to include a correspondingly extended resistance level while reducing current consumption of said memory cell while increasing the length of said load connection path, each of said circuit cells comprises a memory cell in a TFT load type static RAM, each of said load elements comprising a TFT channel having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 8 (depends on 7)

The integrated memory circuit of claim 7 wherein said TFT channel has a length in the range of 0.6 .mu.m to 1.8 .mu.m.

### Claim 9

An integrated memory circuit comprising a plurality of circuit cells each having load elements and MOSFETs formed relative to a semiconductor substrate, said MOSFETs having source/drain domains formed in said substrate with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said memory cells comprising an insulating layer formed on said substrate, a first conductive layer formed on said insulating layer and electrically connected at a first region to at least one of said domains, said first conductive layer extending laterally away from said first region in a first direction to a second region in proximity to an edge of said memory cell laterally spaced from said first region, a second conductive layer spatially insulated from and substantially parallel with said first conductive layer and connected to said first conductive layer at an interconnect formed at said second region between said first and second conductive layers, said second conductive layer having a planar extent extending substantially across said memory cell in a second direction opposite to said first direction, each of said load elements formed in said second conductive layer in a region along said planar extent and extending in said second direction from said interconnect so that said load elements are not present in said second region of said interconnect, said planar extent of said second conductive layer increased due to the extension of said first conductive layer to said cell edge permitting an extended length of said load elements to include a correspondingly extended resistance level while reducing current consumption of said memory cell while increasing the length of said load connection path, each of said circuit cells comprises a memory cell in a TFT load type static RAM, each of said load elements comprising a TFT channel offset having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 10 (depends on 9)

The integrated memory circuit of claim 9 wherein said TFT channel offset has a length in the range of zero to 0.8 .mu.m.

### Claim 11

An integrated memory circuit comprising a plurality of circuit cells each having load elements and MOSFETs formed relative to a semiconductor substrate, said MOSFETs having source/drain domains formed in said substrate with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said memory cells comprising an insulating layer formed on said substrate, a first conductive layer formed on said insulating layer and electrically connected at a first region to at least one of said domains, said first conductive layer extending laterally away from said first region in a first direction to a second region in proximity to an edge of said memory cell laterally spaced from said first region, a second conductive layer spatially insulated from and substantially parallel with said first conductive layer and connected to said first conductive layer at an interconnect formed at said second region between said first and second conductive layers, said second conductive layer having a planar extent extending substantially across said memory cell in a second direction opposite to said first direction, each of said load elements formed in said second conductive layer in a region along said planar extent and extending in said second direction from said interconnect so that said load elements are not present in said second region of said interconnect, said planar extent of said second conductive layer increased due to the extension of said first conductive layer to said cell edge permitting an extended length of said load elements to include a correspondingly extended resistance level while reducing current consumption of said memory cell while increasing the length of said load connection path, each of said circuit cells comprises a memory cell in a TFT load type static RAM, each of said load elements comprising a TFT channel and channel offset having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 12 (depends on 11)

The integrated memory circuit of claim 11 wherein said TFT channel has a length in the range of 0.6 .mu.m to 1.8 .mu.m and said channel offset has a length in the range of zero to 0.8 .mu.m.

### Claim 13

An integrated memory circuit comprising a plurality of circuit cell configurations each having load elements and MOSFETs formed relative to a semiconductor substrate, said MOSFETs having source/drain domains formed in said substrate with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said memory cells comprising a first insulating layer formed on said substrate, a first conductive layer formed on said first insulating layer and connected to at least one of said domains, said first conductive layer functioning, in part, as a gate electrode for at least one of said memory cell MOSFETs, a second insulating layer formed on said first conductive layer, a second conductive layer formed on said second insulating layer and connected to said first conductive layer in a first region in close proximity to said domain, said second conductive layer extending laterally way from said first region in a first direction to a second region in proximity to an edge of said memory cell, a third insulating layer formed on said second conductive layer, a third conductive layer formed on said third insulating layer and partitioned to form an interconnect at said second region and a gate electrode for at least one of said load elements, a fourth insulating layer formed on said third conductive layer, a fourth conductive layer formed on said fourth insulating layer and extending between said second region interconnect to said second layer and across said memory cell in a second direction opposite to said first direction, said planar extent of said fourth conductive layer increased due to the extension of said second conductive layer to said memory cell edge permitting an extended length of said load element to include a correspondingly extended resistance level while reducing current consumption of said memory cell while increasing the length of said load connection path.

### Claim 14 (depends on 13)

The integrated memory circuit of claim 13 wherein each of said circuit cells comprises a memory cell in a TFT load type static RAM, each of said load elements comprising a TFT channel having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 15 (depends on 14)

The integrated memory circuit of claim 14 wherein said TFT channel has a length in the range of 0.6 .mu.m to 1.8 .mu.m.

### Claim 16 (depends on 13)

The integrated memory circuit of claim 13 wherein each of said circuit cells comprises a memory cell in a TFT load type static RAM, each of said load elements comprising a TFT channel offset having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 17 (depends on 16)

The integrated memory circuit of claim 16 wherein said TFT channel offset has a length in the range of zero to 0.8 .mu.m.

### Claim 18 (depends on 13)

The integrated memory circuit of claim 13 wherein each of said circuit cells comprises a memory cell in a TFT load type static RAM, each of said load elements comprising a TFT channel and channel offset having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 19 (depends on 18)

The integrated memory circuit of claim 18 wherein said TFT channel has a length in the range of 0.6 .mu.m to 1.8 .mu.m and said channel offset has a length in the range of zero to 0.8 .mu.m.

### Claim 20

An integrated circuit comprising a plurality of circuit cells each having load elements and transistors formed relative to a semiconductor substrate, said transistors having source/drain domains with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said cells comprising an insulating layer formed on said substrate, a first conductive layer formed on said insulating layer and connected at a first region to at least one of said domains, said first conductive layer extending laterally away from said first region in a first direction to a second region in proximity to an edge of said circuit cell, a second conductive layer spatially insulated from and substantially parallel with said first conductive layer and connected to said first conductive layer at an interconnect formed at said second region between said first and second conductive layers, said second conductive layer having a planar extent extending substantially across said cell in a second direction opposite to said first direction, said planar extent of said second conductive layer increased due to the extension of said first conductive layer to said cell edge permitting an extended length of said load elements to include a correspondingly extended resistance level reducing operational current consumption of said cell while increasing the length of said load connection path to make allowance for impurity migration and prevention of contamination of said load element, said load elements comprising a TFT having a TFT channel and an adjacent channel offset formed in said second conductive layer having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 21 (depends on 20)

The integrated memory circuit of claim 20 wherein said TFT channel has a length in the range of 0.6 .mu.m to 1.8 .mu.m and said channel offset has a length in the range of zero to 0.8 .mu.m.

### Claim 22

An integrated memory circuit comprising a plurality of circuit cells each having load elements and MOSFETs formed relative to a semiconductor substrate, said MOSFETs having source/drain domains formed in said substrate with some of said domains electrically connected through a plurality of conductive and insulating layers formed on said substrate to said load elements comprising a load connection path, said load connection path relative to each of said memory cells comprising an insulating layer formed on said substrate, a first conductive layer formed on said insulating layer and connected at a first region to at least one of said domains, said first conductive layer extending laterally away from said first region in a first direction to a second region in proximity to an edge of said memory cell, a second conductive layer spatially insulated from and substantially parallel with said first conductive layer and connected to said first conductive layer at an interconnect formed at said second region between said first and second conductive layers, said second conductive layer having a planar extent extending substantially across said memory cell in a second direction opposite to said first direction, said planar extent of said second conductive layer increased due to the extension of said first conductive layer to said memory cell edge permitting an extended length of said load elements to include a correspondingly extended resistance level while reducing current consumption of said memory cell while increasing the length of said load connection path, said circuit cells comprising a memory cell in a TFT load type static RAM, each of said load elements comprising a TFT channel and an adjacent channel offset having an extended length and resistance value due, in part, to said extended length to said load connection path.

### Claim 23 (depends on 22)

The integrated memory circuit of claim 22 wherein said TFT channel has a length in the range of 0.6 .mu.m to 1.8 .mu.m and said channel offset has a length in the range of zero to 0.8 .mu.m.