# US 5,348,910 A · Method of manufacturing a semiconductor device and the product thereby > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,348,910 A - Document ID: US5348910A - Status: Granted - Kind: A - Application number: 07/994,312 - Filed: 1992-12-21 - Granted: 1994-09-20 - Earliest claimed: 1991-12-24 - Assignees: Seiko Epson Corporation - Inventors: Isamu Namose - Web page: https://patentgrep.com/patent/US5348910A ## CPC - H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] - H10W 10/0126: {introducing electrical active impurities in local oxidation regions to create channel stoppers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present invention relates to a semiconductor device and a method for manufacturing the same comprising the steps of: forming an oxidation layer on the semiconductor substrate having a predetermined conductivity; introducing impurities having the same conductivity as that of the semiconductor substrate into the semiconductor substrate; forming an anti-oxidation layer on said oxidation layer; removing an arbitrary portion of said anti-oxidation layer; growing the oxidation layer by thermally oxidizing the semiconductor substrate to form the device isolation layer; and removing said anti-oxidation layer. Since the impurities are introduced into the region ranging from the device region to the device isolation region before the anti-oxidation layer is formed, the profile of the impurity concentration distribution in the boundary region between the device region and the device isolation region is smooth. Accordingly it is possible, for example, to prevent narrow channel effects of a transistor and to remove a bird's beak region simply. ## Claims ### Claim 1 A method of manufacturing a MOS-FET semiconductor device having a device isolation layer formed on a semiconductor substrate isolating a device region from a device isolation region, said method comprising the steps of: (a) forming an oxidation layer on the semiconductor substrate having a predetermined conductivity; (b) after step a, introducing impurities having the same conductivity as the semiconductor substrate into the semiconductor substrate, said impurities forming a channel stopper in the device isolation region and controlling a threshold voltage of the MOS-FET device in the device region; (c) after step b, forming an anti-oxidation layer on said oxidation layer; (d) after step c, removing an arbitrary portion of said anti-oxidation layer; (e) after step d, thermally oxidizing the semiconductor substrate to grow a portion of said oxidation layer from which the anti-oxidation layer was removed in step d, to form the device isolation layer; (f) after step e, removing said anti-oxidation layer; and (g) after step f, providing a gate electrode in the device region to form a MOS-FET transistor region, wherein performing step (b) prior to step (c) assures that no peak in a concentration profile of said impurities is formed in the border region between said device region and said device isolation region, thereby preventing the impurities from diffusing into said transistor region and avoiding a narrow channel effect in the MOS-FET device. ### Claim 2 (depends on 1) A semiconductor device manufacturing method according to claim 1, further comprising the step of reducing a bird's beak region at an end of said device isolation layer between said anti-oxidation layer removing step (f) and said gate electrode providing step (g), wherein no peak is formed in a concentration profile of the impurities below the bird's beak, such that a narrow channel effect in the MOS-FET device is prevented when the gate electrode is formed below the bird's beak. ### Claim 3 (depends on 1) A semiconductor device manufacturing method according to claim 1, wherein the impurity implant energy used in said impurity introducing step is at least 40 KeV. ### Claim 4 (depends on 1) A semiconductor device manufacturing method according to claim 1, further comprising the step of controlling an impurity implant energy used in said impurity introducing step (b), to assure the effectiveness of the channel stopper, the impurity implant energy increasing as the thickness of said device isolation layer is increased to prevent excess absorption of said impurities into said device isolation layer. ### Claim 5 (depends on 2) A semiconductor device manufacturing method according to claim 2, further comprising the step of controlling an impurity implant energy used in said impurity introducing step (b), to assure the effectiveness of the channel stopper, the impurity implant energy increasing as the thickness of said device isolation layer is increased to prevent excess absorption of said impurities into said device isolation layer. ### Claim 6 (depends on 1) A semiconductor device manufacturing method according to claim 1, wherein a step of forming a polysilicon layer is inserted between said impurity implant step (b) and said anti-oxidation layer forming step (c). ### Claim 7 (depends on 2) A semiconductor device manufacturing method according to claim 2, wherein a step of forming a polysilicon layer is inserted between said impurity implant step (b) and said anti-oxidation layer forming step (c). ### Claim 8 (depends on 6) A semiconductor device manufacturing method according to claim 6, wherein an impurity implant energy used in said impurity introducing step (c) is at least 40 KeV. ### Claim 9 A method of manufacturing a MOS-FET semiconductor device having a device isolation layer formed on a semiconductor substrate isolating a device region from a device isolation region, said method comprising the steps of: (a) introducing impurities having the same conductivity as the semiconductor substrate into the semiconductor substrate, said impurities acting as a channel stopper in the device isolation region and controlling a threshold voltage of the MOS-FET semiconductor device in the device region; (b) after step (a), forming a first anti-oxidation layer on the semiconductor substrate; (c) after step (b), forming an oxidation layer on said first anti-oxidation layer; (d) after step (c), forming a second anti-oxidation layer on said oxidation layer; (e) after step (d), removing an arbitrary portion of each of said first and second anti-oxidation layers formed to sandwich said oxidation layer; (f) after step (e), forming the device isolation layer by thermally oxidizing the semiconductor substrate; (g) after step (f), removing said first and second anti-oxidation layers formed to sandwich said oxidation layer; and (h) after step (g), providing a gate electrode in the device region to form a MOS-FET transistor region, wherein performing step (a) prior to steps (b), (c) and (d) assures that no peak in a concentration profile of said impurities is formed in a border region between said device region and said device isolation region, thereby preventing the impurities from diffusing into said transistor region and avoiding a narrow channel effect in the MOS-FET device. ### Claim 10 (depends on 9) A semiconductor device manufacturing method according to claim 9, further comprising the step of reducing a bird's beak region at an end of said device isolation layer between the step (g) of removing said first and second anti-oxidation layers formed to sandwich said oxidation layer and the step (h) of providing a gate electrode, wherein no peak is formed in a concentration profile of the impurities below the bird's beak, and a narrow channel effect in the MOS-FET device is prevented when the gate electrode is formed below the bird's beak. ### Claim 11 (depends on 10) A semiconductor device manufacturing method according to claim 10, further comprising the step of controlling an impurity implant energy used in said impurity introducing step (a), to assure the effectiveness of the channel stopper, the impurity implant energy increasing as the thickness of said device isolation layer is increased to prevent excess absorption of said impurities into said device isolation layer. ### Claim 12 (depends on 9) A semiconductor device manufacturing method according to claim 9, wherein the impurity implant energy used in said impurity introducing step is at least 40 KeV or more. ### Claim 13 (depends on 1) A semiconductor device manufacturing method according to claim 1, wherein an impurity implant energy used in said impurity introducing step is at least 80 kev. ### Claim 14 (depends on 2) A semiconductor device manufacturing method according to claim 2, wherein an impurity implant energy used in said impurity introducing step is at least 80 kev. ### Claim 15 (depends on 4) A semiconductor device manufacturing method according to claim 4, wherein an impurity implant energy used in said impurity introducing step is at least 80 kev. ### Claim 16 (depends on 5) A semiconductor device manufacturing method according to claim 5, wherein an impurity implant energy used in said impurity introducing step is at least 80 kev. ### Claim 17 (depends on 6) A semiconductor device manufacturing method according to claim 6, wherein an impurity implant energy used in said impurity introducing step is at least 80 kev. ### Claim 18 (depends on 9) A semiconductor device manufacturing method according to claim 9, wherein an impurity implant energy used in said impurity introducing step is at least 80 kev.