# US 5,348,907 A · Method of fabricating of semiconductor device by forming two electrically insulated wells of the same type electroconductivity on semiconductor substrate

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- Number: US 5,348,907 A
- Document ID: US5348907A
- Status: Granted
- Kind: A
- Application number: 08/054,335
- Filed: 1993-04-28
- Granted: 1994-09-20
- Earliest claimed: 1992-04-28
- Assignees: NEC Corporation
- Inventors: Takahisa Migita
- Web page: https://patentgrep.com/patent/US5348907A

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 10/00: Static random access memory [SRAM] devices
- H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A fabrication method of a semiconductor device in which the characteristic deterioration of the device due to electric charges generating in the fabrication process can be prevented. A first well of a first electroconductive type is formed on a semiconductor substrate of the first electroconductive type. The first well is surrounded by a semiconductor layer of a second electroconductive type opposite to the first electroconductive type. A second well of the first electroconductive type, which is insulated from the first well and connected to the substrate, is formed on the substrate. An electroconductive layer for connecting the first and second wells. The electroconductive layer is partially removed to insulate the first and second wells after finishing a process having a possibility for generating electric charges on the substrate.

## Claims

### Claim 1

A fabrication method of a semiconductor device comprising the steps of:
forming a first well of a first electroconductive type on one main surface of a semiconductor substrate of said first electroconductive type which is surrounded by a semiconductor layer of a second electroconductive type opposite to said first electroconductive type;
forming a second well of said first electroconductive type on the main surface of said substrate which is electrically insulated from said first well and is electrically connected to said substrate;
forming an electroconductive layer which connects said first well and said second well to each other on an insulator layer between said first and second wells; and
partially removing said electroconductive layer to electrically insulate said first and second well from each other after finishing a process which generates electric charges on the substrate.

### Claim 2 (depends on 1)

The method according to claim 1, wherein a buried layer of said second electroconductive type formed in said substrate and an epitaxial layer of said second electroconductive type formed on said buried layer are included,
said first well being formed in said epitaxial layer, and said buried layer and said epitaxial layer being connected to each other in the periphery of said first well.

### Claim 3 (depends on 2)

The method according to claim 2, and further including the steps of:
forming an interlayer insulation layer of said first and second wells;
forming a passivation layer on said interlayer insulation layer; and
making a hole extending through said interlayer insulation layer and said passivation layer to said electroconductive layer; and
said step of electrically insulating said first and second wells being realized by applying an irradiating beam to said electroconductive layer through said hole to partially fuse and remove said electroconductive layer at said hole.

### Claim 4 (depends on 3)

The method according to claim 3, wherein said first well is used for an MOSFET constituting a memory cell and said second well is used for a peripheral circuit of said memory cell.

### Claim 5 (depends on 4)

The method according to claim 4, wherein said electroconductive layer is connected to a source/drain region of said MOSFET.

### Claim 6 (depends on 4)

The method according to claim 4, wherein said electroconductive layer is connected to a gate electrode of said MOSFET.

### Claim 7 (depends on 4)

The method according to claim 4, wherein said electroconductive layer is connected to one of said first well and second well which is not used as a source/drain region of said MOSFET.

### Claim 8

A fabrication method of a semiconductor device comprising the steps of:
forming a first well of a first electroconductive type on one main surface of a semiconductor substrate of said first electroconductive type which is surrounded by a semiconductor layer of a second electroconductive type opposite to said first electroconductive type;
forming a second well of said first electroconductive type of the main surface of said substrate which is electrically insulated from said first well and is electrically connected to said substrate;
forming an electroconductive layer which connects said first well and said second well to each other on an insulator layer between said first and second wells; and
partially removing said electroconductive layer to electrically insulate said first and second wells from each other after finishing a process which generates electric charges on the substrate;
wherein said first well is used for an MOSFET constituting a memory cell and said second well is used for a peripheral circuit of said memory cell, and said electroconductive layer is connected to a gate electrode of said MOSFET.