# US 5,348,905 A · Method of making diffused buried plate trench DRAM cell array

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- Number: US 5,348,905 A
- Document ID: US5348905A
- Status: Granted
- Kind: A
- Application number: 08/112,406
- Filed: 1993-08-26
- Granted: 1994-09-20
- Earliest claimed: 1992-01-09
- Assignees: International Business Machines Corporation
- Inventors: Donald M. Kenney
- Web page: https://patentgrep.com/patent/US5348905A

## CPC

- H10B 12/37: {the capacitor being at least partially in a trench in the substrate}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A high density substrate plate DRAM cell memory device and process are described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by lateral outdiffusion from the sidewalls of the deep trenches and partially formed by an N-well surface diffusion which entirely surrounds the DRAM array region.

## Claims

### Claim 1

The method of making a dynamic random access memory device comprising the steps of:
providing a semiconductor substrate of a first conductivity type;
forming a plurality of deep trenches in a matrix pattern on a top surface of said substrate;
diffusing a second conductivity type impurity from the lower portion of the depth of said deep trenches into said substrate to form a continuous buried diffused region of a second conductivity type across the entire extent of the matrix pattern;
forming a dielectric layer on the inside of said deep trenches and filling said trenches with a conductive electrode material;
forming around the perimeter of said matrix pattern a diffused surface region of said second conductivity type having a depth so as to physically and electrically isolate a portion of the substrate within the matrix pattern above said continuous buried diffused region; and
forming within the isolated portion of the matrix pattern a plurality of semiconductor devices for coupling signals to and from said conductive electrode material within at least some of said deep trenches.

### Claim 2 (depends on 1)

The method of claim 1 wherein a diffusion barrier collar is provided in the upper portion of said deep trenches.

### Claim 3 (depends on 1)

The method of making a dynamic random access memory device of claim 1 wherein the step of forming a dielectric layer on the inside of said deep trenches includes the step of forming a thick dielectric collar at the top of said deep trenches.

### Claim 4 (depends on 2)

The method of claim 2 wherein the diffusion barrier collar is removed prior to the forming of a dielectric layer inside of said deep trenches.

### Claim 5 (depends on 3)

The method of making a dynamic random access memory device of claim 3 wherein the step of forming a plurality of deep trenches includes the steps of forming a plurality of shallow trenches in said substrate, forming a sidewall protecting layer on the sidewalls of said shallow trenches, extending the depth of said shallow trenches to form said deep trenches, placing a source of impurity dopant material at least on the lower portion of the sidewalls of the extended deep trenches.

### Claim 6 (depends on 5)

The method of making a dynamic random access memory device of claim 5 wherein the source of dopant material used to form the continuous buried diffused region is arsenic.

### Claim 7 (depends on 5)

The method of making a dynamic random access memory device of claim 5 wherein the source of dopant material used to form the continuous buried diffused region is an arsenic containing glass layer.