# US 5,348,901 A · Interconnect and resistor for integrated circuits

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- Number: US 5,348,901 A
- Document ID: US5348901A
- Status: Granted
- Kind: A
- Application number: 07/911,167
- Filed: 1992-07-09
- Granted: 1994-09-20
- Earliest claimed: 1991-09-30
- Assignees: SGS-Thomson Microelectronics S.A.
- Inventors: Fusen E. Chen; Girish A. Dixit; Robert O. Miller
- Web page: https://patentgrep.com/patent/US5348901A

## CPC

- H10D 1/47: Resistors having no potential barriers
- H10B 10/15: {comprising a resistor load element}
- H10W 20/066: {by forming silicides of refractory metals}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.

## Claims

### Claim 1

A method for forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of:
forming a first conductive layer wherein the first conductive layer has a first region of a first conductivity type and a second region of a second conductivity type wherein a junction is formed between the first and the second regions;
forming a first oxide region over the second region of the first conductive layer and the junction;
depositing an undoped oxide layer over the integrated circuit;
performing an etchback of the undoped oxide layer to form sidewall oxide spacers on the sidewalls of the first oxide region covering the junction and a portion of the first region of the first conductive layer adjacent to the junction; and
forming a silicide region over the first region of the first conductive layer not covered by the sidewall oxide spacer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first conductive layer is a polysilicon layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first conductive layer is a polycide layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first conductive layer's first region is implanted with a N-type dopant.

### Claim 5 (depends on 4)

The method of claim 4, wherein the N-type dopant is arsenic.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first conductive layer's second region is implanted with a P-type dopant.

### Claim 7 (depends on 6)

The method of claim 6, wherein the P-type dopant is boron.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first conductive layer has a thickness of between approximately 500-2000 angstroms.

### Claim 9 (depends on 1)

The method of claim 1, wherein a second oxide region is disposed under the first conductive layer and wherein the second oxide region has an opening therethrough exposing a portion of an underlying second conductive layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first conductive layer is further disposed over the exposed portion of the second conductive layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein the silicide forming step further comprises the steps of:
forming a metal silicide forming layer over the integrated circuit;
annealing the metal silicide forming layer; and,
removing unreacted metal from the metal silicide forming layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the metal silicide forming layer is deposited to a depth of between approximately 200-1000 angstroms.

### Claim 13 (depends on 12)

The method of claim 12, wherein the metal silicide forming layer is a refractory metal.

### Claim 14 (depends on 13)

The method of claim 13, wherein the refractory metal is titanium.

### Claim 15

A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of:
forming a lightly doped first conductive layer having a conductivity of a first type;
forming a first oxide layer over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer;
using the first oxide layer as a mask, implanting the exposed portion of the first conductive layer with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask;
depositing an undoped oxide layer over the integrated circuit;
performing an etchback of the undoped oxide layer to form a sidewall oxide spacer of the sidewall of the first oxide layer; and
forming a silicide over the exposed portion of the first conductive layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first conductive layer is disposed over a portion of a second conductive layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first conductive layer is a polysilicon layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein the first conductive layer is a polycide layer.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first conductivity type is P-type.

### Claim 20 (depends on 15)

The method of claim 15, wherein the second conductivity type is N-type.

### Claim 21 (depends on 15)

The method of claim 15, wherein the first conductive layer has a thickness of between approximately 500 to 2000 angstroms.

### Claim 22 (depends on 15)

The method of claim 15, wherein the first oxide layer and second oxide region have a thickness of between approximately 900 to 2000 angstroms.

### Claim 23 (depends on 15)

The method of claim 15, wherein the silicide forming step further comprises the steps of:
forming a metal silicide forming layer over the integrated circuit;
annealing the metal silicide forming layer; and,
removing any unreacted metal from the metal silicide forming layer.

### Claim 24 (depends on 23)

The method of claim 23, wherein the metal silicide forming layer is deposited to a depth of between approximately 200-1000 angstroms.

### Claim 25 (depends on 24)

The method of claim 24, wherein the metal silicide forming layer is a refractory metal.

### Claim 26 (depends on 25)

The method of claim 25, wherein the refractory metal is titanium.

### Claim 27

A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of:
forming a first conductive layer wherein the first conductive layer has a first region of a first conductivity type and a second region of a second conductivity type wherein a junction is formed between the first and the second regions;
forming a first oxide region over the first region of the first conductive layer and the junction;
depositing an undoped oxide layer over the integrated circuit;
patterning and etching the undoped oxide layer to form an undoped oxide region over the first oxide region, the junction and a portion of the first region of the first conductive layer adjacent to the junction; and
forming a silicide region over the second region of the first conductive layer not covered by the undoped oxide layer.

### Claim 28

A method of forming a polycrystalline silicon resistive load element in a semiconductor integrated circuit, comprising the steps of:
forming a lightly doped first conductive layer having a conductivity of a first type;
forming a first oxide layer over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer;
using the first oxide layer as a mask, implanting the exposed portion of the first conductive layer with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask;
depositing an undoped oxide layer over the integrated circuit;
patterning and etching the undoped oxide layer to again expose an implanted portion of the first conductive layer; and
forming a silicide over the exposed portion of the first conductive layer.