# US 5,347,634 A · System and method for directly executing user DMA instruction from user controlled process by employing processor privileged work buffer pointers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,347,634 A - Document ID: US5347634A - Status: Granted - Kind: A - Application number: 07/494,008 - Filed: 1990-03-15 - Granted: 1994-09-13 - Earliest claimed: 1990-03-15 - Assignees: Hewlett-Packard Company - Inventors: Russ W. Herrell; Curtis R. McAllister; Dong Y. Kuo; Christopher G. Wilcox - Web page: https://patentgrep.com/patent/US5347634A ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, establishes work buffers for each user process, and retrieves blocks of data from the work buffers at the user's is request, rather than at the request of the kernel software. This is accomplished by establishing work buffers for each user process which are locked into physical memory. The controlling user process will then fill one work buffer, acquire the device semaphore, start physical DMA on the locked buffer, and then start filling another buffer. Memory integrity is maintained by allowing the user to access the work buffers for DMA without knowing their physical location in memory, via work buffer pointers from work buffer pointer registers which correspond to each work buffer for each user process. These work buffer pointer registers are privileged and are updated by the host processor for each new controlling user process. ## Claims ### Claim 1 A device for transferring data processing commands and associated data between a user's host system, having a main memory and host processor, and an external data processing system via user controlled direct memory access (DMA) comprising: a work buffer in said main memory which is locked for a DMA controlling user process of said host processor, said work buffer storing said data processing commands and associated data for said DMA controlling user process; a work buffer pointer register containing a work buffer pointer to said work buffer for said DMA controlling user process, said work buffer pointer being unique to said DMA controlling user process and said host processor having privileged access to said work buffer pointer register whereby said work buffer pointer is unmodifiable by said DMA controlling user process either directly or indirectly; and means responsive to a user DMA instruction from said DMA controlling user process for reading data processing commands and associated data specified in said user DMA instruction from said work buffer starting at the address pointed to by said work buffer pointer and for transferring, via DMA, said data processing commands and associated data from said work buffer to said external data processing system. ### Claim 2 (depends on 1) A device as in claim 1, wherein said external data processing system comprises a communications network. ### Claim 3 (depends on 1) A device as in claim 1, wherein said external data processing system comprises a graphics subsystem of said user's host system. ### Claim 4 (depends on 3) A device as in claim 3, wherein said data processing commands comprise graphics commands and said associated data comprises graphics primitives. ### Claim 5 (depends on 4) A device as in claim 4, wherein two work buffers are created for each of said plurality of user processes being processed by said host processor, whereby one work buffer may be read while the other is written. ### Claim 6 (depends on 5) A device as in claim 5, wherein two work buffer pointer registers are provided, one for each work buffer, whereby each work buffer pointer register contains a work buffer pointer to different ones of said work buffers, each work buffer pointer being unique to the DMA controlling user process. ### Claim 7 (depends on 6) A device as in claim 6, wherein each of said work buffers comprises 512 32-bit words, each work buffer being aligned so as not to cross a page boundary of said main memory. ### Claim 8 (depends on 7) A device as in claim 7, wherein a page in said main memory containing said work buffers is locked by the DMA controlling user process. ### Claim 9 (depends on 6) A device as in claim 6, wherein said work buffer pointer registers may not be accessed by the DMA controlling user process and are updated by said host processor to include updated work buffer pointers when the DMA controlling user process is swapped out. ### Claim 10 (depends on 9) A device as in claim 9, wherein said work buffer pointer registers are mapped onto at least one privileged page in said main memory so as to prevent access by the DMA controlling user process. ### Claim 11 (depends on 6) A device as in claim 6, wherein said reading and transferring means comprises means responsive to said user DMA instruction for specifying which of said work buffer pointer registers a work buffer pointer is to be read from and hence which work buffer said data processing commands and associated data are to be read from. ### Claim 12 (depends on 11) A device as in claim 11, wherein said specifying means further specifies the number of words to be read from the specified work buffer. ### Claim 13 (depends on 12) A device as in claim 12, wherein said specifying means comprises a control register which initiates said data reading and transferring when a user DMA instruction requesting DMA is received from the DMA controlling user process. ### Claim 14 (depends on 13) A device as in claim 13, wherein said control register includes status means for determining at least one of whether a data reading and transferring process is in progress, whether an error occurred in a previous data reading and transferring process, which of said work buffer pointer ### Claim 15 (depends on 13) A device as in claim 13, wherein said user DMA instruction includes instructions from the user as to which of said work buffers to read, the number of words to be read and when said read is to occur. ### Claim 16 (depends on 1) A device as in claim 1, wherein the work buffer pointer for the DMA controlling user process points to the starting address of the work buffer for the DMA controlling user process. ### Claim 17 (depends on 1) A device as in claim 1, wherein each work buffer pointer is an address offset used to determine an address within the corresponding work buffer. ### Claim 18 (depends on 1) A device as in claim 1, wherein said reading and transferring means comprises a bidirectional bus buffer and an input/output bus for connecting said external data processing system to said host processor and said main memory. ### Claim 19 (depends on 18) A device as in claim 18, wherein said bidirectional bus buffer provides noninterfering bidirectional data transfer between said main memory and said external data processing system in response to said user DMA instruction. ### Claim 20 (depends on 1) A device as in claim 1, further comprising synchronizing means for synchronizing said host processor to reads by said reading and transferring means. ### Claim 21 (depends on 1) A device as in claim 1, further comprising means for providing data consistency in said main memory between subsequent reads by said reading and transferring means by selective use of data snooping and user controlled data flushing of a cache of said main memory. ### Claim 22 A device for transferring graphics commands and graphics primitives between a user's host system, having a main memory and a host processor, and a graphics processing subsystem via user controlled direct memory access (DMA) comprising: at least two work buffers in said main memory which are locked for a DMA controlling user process of said host processor, each work buffer selectively storing said graphics commands and graphics primitives for said DMA controlling user process; work buffer pointer registers respectively containing work buffer pointers to different ones of said work buffers for said DMA controlling user process, each work buffer pointer being unique to said DMA controlling user process and said host processor having privileged access to said work buffer pointer registers whereby each work buffer pointer is unmodifiable by said DMA controlling user process either directly or indirectly; and means responsive to a user DMA instruction from said DMA controlling user process for reading graphics commands and graphics primitives specified in said user DMA instruction from a work buffer selected by the user at the address pointed to by the corresponding work buffer pointer, and for transferring, via DMA, said graphics commands and graphics primitives from said selected work buffer to said graphics subsystem. ### Claim 23 (depends on 22) A device as in claim 22, wherein said work buffer pointer registers may not be accessed by the DMA controlling user process and are updated by said host processor to include updated work buffer pointers when the DMA controlling user process is swapped out. ### Claim 24 (depends on 23) A device as in claim 23, wherein said work buffer pointer registers are mapped onto at least one privileged page in said main memory so as to prevent access by the DMA controlling user process. ### Claim 25 (depends on 22) A device as in claim 22, wherein said reading and transferring means comprises means responsive to said user DMA instruction for specifying which of said work buffer pointer registers a work buffer pointer is to be read from and hence which work buffer said graphics commands and graphics primitives are to be read from. ### Claim 26 (depends on 25) A device as in claim 25, wherein said specifying means further specifies the number of words to be read from the specified work buffer. ### Claim 27 (depends on 26) A device as in claim 26, wherein said specifying means comprises a control register which initiates said data reading and transferring when a user DMA instruction requesting DMA is received from the DMA controlling user process. ### Claim 28 (depends on 27) A device as in claim 27, wherein said control register includes status means for determining at least one of whether a data reading and transferring process is in progress, whether an error occurred in previous data reading and transferring process, which of said work buffer pointer registers is currently being read and the number of words currently being transferred. ### Claim 29 (depends on 27) A device as in claim 27, wherein said user DMA instruction includes instructions from the user as to which of said work buffers to read, the number of words to be read and when said read is to occur. ### Claim 30 (depends on 22) A device as in claim 22, wherein the work buffer pointers for the DMA controlling user process point to the starting address of the corresponding work buffer for the DMA controlling user process. ### Claim 31 (depends on 22) A device as in claim 22, wherein each work buffer pointer is an address offset used to determine an address within the corresponding work buffer. ### Claim 32 (depends on 22) A device as in claim 22, wherein said reading and transferring means comprises a bidirectional bus buffer and an input/output bus for connecting said graphics subsystem to said host processor and said main memory. ### Claim 33 (depends on 32) A device as in claim 32, wherein said bidirectional bus buffer provides noninterfering bidirectional data transfer between said main memory and said graphics subsystem in response to said user DMA instruction. ### Claim 34 (depends on 22) A device as in claim 22, further comprising synchronizing means for synchronizing said host processor to reads by said reading and transferring means. ### Claim 35 (depends on 22) A device as in claim 22, further comprising means for providing data consistency in said main memory between subsequent reads by said reading and transferring means by selective use of data snooping and user controlled data flushing of a cache of said main memory. ### Claim 36 A method for providing user controlled direct memory access (DMA) by an external data processing system to data stored in a main memory of a user's host system having a host processor in response to a user DMA command, comprising the steps of: defining a work buffer in said main memory for each of a plurality of user processes being processed by the user's host system; writing the user's data processing commands and associated data in a work buffer which is locked by a DMA controlling user process of said user's host system; defining a work buffer pointer register for said DMA controlling user process, said work buffer pointer register containing a work buffer pointer to said work buffer locked by said DMA controlling user process, said work buffer pointer being unique to said DMA controlling user process and said host processor having privileged access to said work buffer pointer register whereby said work buffer pointer is unmodifiable by said DMA controlling user process either directly or indirectly; reading, in response to said DMA command from said DMA controlling user process, said data processing commands and associated data from said work buffer locked by said DMA controlling user process starting at an address pointed to by the work buffer pointer for said DMA controlling user process; and transferring, via DMA, said data processing commands and associated data from said work buffer locked by said DMA controlling user process to said external data processing system. ### Claim 37 (depends on 36) A method as in claim 36, wherein said external data processing system comprises a graphics subsystem of said user's host system, said user's data processing command is a graphics command and said associated data comprises graphics primitives. ### Claim 38 (depends on 37) A method as in claim 37, wherein said work buffer defining step defines two work buffers for each user process such that one work buffer may be read while the other is written. ### Claim 39 (depends on 38) A method as in claim 38, wherein said work buffer pointer register defining step defines two work buffer pointer registers for each user process, one for each work buffer, each work buffer pointer register containing a work buffer pointer to different ones of said work buffers and each work buffer pointer being unique to the DMA controlling user process. ### Claim 40 (depends on 39) A method as in claim 39, wherein said work buffer pointer register defining step includes the steps of mapping the work buffer pointer registers onto a privileged memory page so as to be inaccessible to the DMA controlling user process and updating the work buffer pointers in said work buffer pointer registers to include updated work buffer pointers when the DMA controlling user process is swapped out. ### Claim 41 (depends on 40) A method as in claim 40, including the further steps of specifying which work buffer to read said data processing commands and associated data from and reading the work buffer pointer from the work buffer pointer register corresponding to the specified work buffer. ### Claim 42 (depends on 41) A method as in claim 41, wherein said specifying step includes the step of specifying the number of words to be read from the specified work buffer during said reading step. ### Claim 43 (depends on 36) A method as in claim 36, comprising the further step of determining the address of said data processing commands and associated data in said work buffer by using said work buffer pointer as an index within said work buffer. ### Claim 44 (depends on 36) A method as in claim 36, comprising the further step of synchronizing the DMA controlling user process to said reading step. ### Claim 45 (depends on 36) A method as in claim 36, comprising the further step of flushing a cache memory of said main memory before said data transferring step is attempted. ### Claim 46 A method for providing user controlled direct memory access (DMA) by an external data processing system to data stored in a main memory of a user's host system having a host processor in response to a user DMA command, comprising the steps of: defining at least two work buffers in said main memory for each of a plurality of user processes being processed by the user's host system; acquiring a memory lock on said work buffers for a DMA controlling user process being implemented by said user's host system; writing the user's data processing commands and associated data to one of the work buffers defined for said DMA controlling user process; defining work buffer pointer registers respectively containing work buffer pointers to different ones of said work buffers for said DMA controlling user process, each work buffer pointer being unique to said DMA controlling user process and said host processor having privileged access to said work buffer pointer registers whereby each work buffer pointer is unmodifiable by said DMA controlling user process either directly or indirectly; and issuing said user DMA command to start DMA from a selected one of said work buffers; reading said data processing commands and associated data from the selected work buffer starting at an address pointed to by the work buffer pointer corresponding to the selected work buffer for said DMA controlling user process; and transferring said data processing commands and associated data from said selected work buffer to said external data processing system. ### Claim 47 (depends on 46) A method as in claim 46, wherein said user's data processing commands and associated data are written to the other of said work buffers when said selected work buffer is being read. ### Claim 48 (depends on 47) A method as in claim 47, wherein said work buffers may be swapped by issuing another user DMA command to start DMA from the other of said work buffers.