# US 5,347,559 A · Apparatus and method of data transfer between systems using different clocks

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,347,559 A
- Document ID: US5347559A
- Status: Granted
- Kind: A
- Application number: 07/998,714
- Filed: 1992-12-30
- Granted: 1994-09-13
- Earliest claimed: 1992-12-30
- Assignees: Digital Equipment Corporation
- Inventors: Thomas B. Hawkins; William Bruckert; Thomas D. Bissett
- Web page: https://patentgrep.com/patent/US5347559A

## CPC

- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 11/1633: {using mutual exchange of the output between the redundant processing components}
- G06F 11/1645: {and the comparison itself uses redundant hardware}
- G06F 11/1658: {Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit}
- G06F 11/1679: {at clock signal level}
- G06F 11/1683: {at instruction level}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/4243: {with synchronous protocol}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- G06F 11/006: {Identification (G06F11/2289 takes precedence)}
- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G06F 11/1044: {with specific ECC/EDC distribution}
- G06F 11/1604: {where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware}
- G06F 11/1654: {where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O}
- G06F 11/20: using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F 11/2205: {using arrangements specific to the hardware being tested}
- H03D 13/003: {in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means}
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66)

## Abstract

According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

## Claims

### Claim 1

Apparatus comprising:
means for providing a data value;
a counter;
means for detecting a selected state of said counter to load said data value into said counter in accordance with said detected state of said counter;
means for storing data bits with the logic state of selected ones of said bits corresponding to a temporal relationship of pairs of pulses of clock signals for which valid data transfers can occur
means responsive to output signals from said counter for selectively providing said selected bits as an enable signal in accordance with the state of said counter; and
at least one recirculating state device fed by said enable signal and said clock signals to selectively permit or inhibit transfer of data fed to said recirculating state device in accordance with the state of said enable signal.

### Claim 2 (depends on 1)

The apparatus as recited in claim 1 wherein said means for providing a data value is a register fed by said data.

### Claim 3 (depends on 2)

The apparatus as recited in claim 2 further comprising:
a second register;
a second counter;
second means for detecting a selected state of said second counter to load data contained in said second register into said second counter in accordance with said detected state of said second counter;
second means response to output signals from said second counter for selectively providing a second enable signal in accordance with the state of said second counter; and wherein
said recirculating state device is fed by said first and second enable signals to selectively permit or inhibit transfer of data fed to said recirculating state device in accordance with the state of said enable signals.

### Claim 4 (depends on 3)

The apparatus as recited in claim 3 wherein said recirculating state device further comprises:
means responsive to data associtated with a first clock signal for transferring said data in association with a second, different clock signal.

### Claim 5 (depends on 4)

The apparatus as recited in claim 4 wherein said recirculating state device further comprises:
means responsive to data associtated with said second clock signal for transferring said data in association with said first clock signal.

### Claim 6

Apparatus comprising:
a first register containing a first data string;
a first counter;
means for detecting a selected state of said first counter to load the data contained in said first register into said counter in accordance with said detected state of said counter;
means response to output signals from said first counter for selectively providing an enable signal in accordance with the state of said first counter;
a second register containing a second data string;
a second counter;
means for detecting a selected state of said second counter to load the data contained in said register into said counter in accordance with said detected state of said second counter;
means, responsive to outputs signals from said second counter, for selectively providing a second enable signal in accordance with the state of said second counter; and
a recirculating state device fed by said enable signals to selectively permit or inhibit transfer of data fed to said recirculating state device in accordance with the state of said enable signals.

### Claim 7 (depends on 6)

The apparatus as recited in claim 6 wherein said recirculating state device is fed by a pair of data streams a first one thereof associated with a first clock signal and a second one thereof associated with a second clock signal.

### Claim 8 (depends on 7)

The apparatus as recited in claim 7 further comprising:
means for determining when corresponding asserting edges of pulses of said first and second clock signals are disposed to permit data transfers to occur by setting bite in said data coresponding to said enable signals.

### Claim 9

Apparatus, comprising:
a first down counter;
a first register containing data representative of a maximum value count of said counter;
means for detecting a selected state of said first counter to load the data contained in said first register into said first counter to restart said counter at a said maximum value count;
means responsive to states of said first counter for providing an enable signal from a list of states corresponding to valid states for said counter for which a transfer of data fed to said apparatus can occur;
a second down counter;
a second register containing data representative of a second maximum value count of said second counter;
means for detecting a selected state of said second counter to load the data contained in said second register into said second counter to restart said counter at a said second maximum value count;
means, responsive to states of said second counter, for providing a second enable signal from a second list of states corresponding to valid states for said second counter for which a transfer of data fed to said apparatus can occur;
means for providing a recirculating state device responsive to said first and second selected enable signals, a pair of clock signals, and data associated with a first one of said pair of clock signals for outputting said data in association with a second one of said pair of clock signals when said enable signals are in a state indicating that a transfer of said data can occur.

### Claim 10 (depends on 9)

The apparatus as recited in claim 9 further comprising:
means for providing a second recirculating state device responsive to said first and second selected enable signals, the pair of clock signals, and data associated with said second one of said pair of clock signals for outputting said data in association with said first one of said pair of clock signals when said enable signals are in a state indicating that a transfer of said data can occur.