# US 5,347,520 A · Boundary-scan enable cell with non-critical enable path

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- Number: US 5,347,520 A
- Document ID: US5347520A
- Status: Granted
- Kind: A
- Application number: 07/761,607
- Filed: 1991-09-18
- Granted: 1994-09-13
- Earliest claimed: 1991-09-18
- Assignees: NCR Corporation
- Inventors: David L. Simpson; Wilson E. Smoak, III
- Web page: https://patentgrep.com/patent/US5347520A

## CPC

- G01R 31/318541: {Scan latches or cell details}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A boundary-scan enable cell which includes critical and non-critical enable paths without adding an extra layer of logic. The boundary-scan cell includes a multiplexer, a critical enable path which transmits critical enable terms coupled to a first multiplexer input, a sampling circuit which transmits non-critical terms coupled to a second multiplexer input, and a non-critical term path which transmits non-critical masking terms, coupled to the shift input of the multiplexer. Non-critical terms at the shift input are mimicked at the second input. Provision is also made for a test control circuit and a circuit for monitoring critical and non-critical terms.

## Claims

### Claim 1

A boundary-scan cell for testing a system logic and its pin connections comprising:
a monitoring circuit including a NOR gate having critical enable term and non-critical term inputs and having a term output and a test output for comparison with a twin cell;
a first multiplexer having critical enable term, non-critical term, and shift inputs;
a sampling circuit coupled between the term output of the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input and a previous cell contents input, a shift register coupled to the output of the second multiplexer including an inverter coupled to the output of the second multiplexer and a D-type flip-flop coupled to the output of the inverter, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer; and
a test control circuit including a first subcircuit coupled between the latch output and the non-critical term input of the first multiplexer including a first NAND gate having latch and first test inputs, a second NAND gate having first NAND gate and second test inputs, and a third NAND gate having second NAND gate and third test input and a non-critical term output, and a second subcircuit coupled between the system logic and the shift input of the first multiplexer including an OR gate having non-critical term and third test inputs.

### Claim 2

A device for isolating an input/output pad from an integrated circuit comprising:
a monitoring circuit including a NOR gate having critical enable term and non-critical term inputs and having a term output and a test output for comparison with a twin cell;
a first multiplexer having critical term, non-critical term, and shift inputs, the device selecting the critical term input during normal operation of the integrated circuit and the non-critical term input during both test and default operation of the integrated circuit;
a sampling circuit coupled between the term output of the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input and a previous device contents input, a shift register coupled to the output of the second multiplexer, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer; and
a test control circuit coupled between the integrated circuit and the shift inputs of the first multiplexer including an OR gate having non-critical term and third test inputs.

### Claim 3 (depends on 2)

The device as recited in claim 2, wherein the test control circuit further comprises:
a first subcircuit coupled between the latch output and the non-critical term input of the first multiplexer including a first NAND gate having latch and first test inputs, a second NAND gate having first NAND gate and second test inputs, and a third NAND gate having second NAND gate and third test input and a non-critical term output.