# US 5,347,483 A · Non-volatile associative memory with low transistor count

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- Number: US 5,347,483 A
- Document ID: US5347483A
- Status: Granted
- Kind: A
- Application number: 08/027,132
- Filed: 1993-03-05
- Granted: 1994-09-13
- Earliest claimed: 1992-03-06
- Assignees: Sharp Kabushiki Kaisha
- Inventors: Yasuo Torimaru
- Web page: https://patentgrep.com/patent/US5347483A

## CPC

- G11C 15/046: {using non-volatile storage elements}
- G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A non-volatile memory cell is disclosed. The non-volatile memory cell includes first and second selecting transistors, first and second non-volatile memory transistors for storing data in a non-volatile manner, and first and second output transistors. A gate of the first selecting transistor and a gate of the second selecting transistor are connected to a word line. A drain of the first selecting transistor is connected to a first bit line, and a drain of the second selecting transistor is connected to a second bit line. A drain of the first non-volatile memory transistor is connected to a source of the first selecting transistor. A drain of the second non-volatile memory transistor is connected to a source of the second selecting transistor. A source of the first non-volatile memory transistor and a source of the second non-volatile memory transistor are connected to a source line. A gate of the first non-volatile memory transistor and a gate of the second non-volatile memory transistor are connected to a control gate line. A drain of the first output transistor and a drain of the second output transistor are connected to a first output line. A source of the first output transistor and a source of the second output transistor are connected to a second output line. A gate of the first output transistor is connected to a drain of the first non-volatile memory transistor. A gate of the second output transistor is connected to a drain of the second non-volatile memory transistor.

## Claims

### Claim 1

A non-volatile memory cell comprising:
first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line;
first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and
first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being directly connected to a first output line, a source of said first output transistor and a source of said second output transistor being directly connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor.

### Claim 2 (depends on 1)

A non-volatile memory cell according to claim 1, wherein said first and second non-volatile memory transistors are N-channel non-volatile memory transistors of floating gate type.

### Claim 3

A non-volatile associative memory device including a plurality of memory cells, each of said memory cells comprising:
first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line;
first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and
first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being directly connected to a first output line, a source of said first output transistor and a source of said second output transistor being directly connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor.

### Claim 4

A non-volatile associative memory device including a plurality of memory cells, each of said memory cells comprising:
first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line;
first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line; and
first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being connected to a first output line, a source of said first output transistor and a source of said second output transistor being connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor,
wherein said memory cells are connected in series via said first and second output lines.

### Claim 5 (depends on 3)

A non-volatile associative memory device according to claim 3, wherein said memory cells are connected in parallel via said first and second output lines.

### Claim 6 (depends on 4)

A non-volatile associative memory device according to claim 4, wherein said first and second non-volatile memory transistors are N-channel non-volatile memory transistors of a floating gate type.

### Claim 7 (depends on 4)

A non-volatile associative memory device according to claim 4, wherein said first and second selecting transistors, said first and second non-volatile memory transistors, and said first and second output transistors have a same type polarity.

### Claim 8 (depends on 7)

A non-volatile associative memory device according to claim 7, wherein said first and second selecting transistors, said first and second non-volatile memory transistors, and said first and second output transistors are each N-channel transistors.