# US 5,347,472 A · Precharge circuitry and bus for low power applications

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- Number: US 5,347,472 A
- Document ID: US5347472A
- Status: Granted
- Kind: A
- Application number: 08/070,651
- Filed: 1993-05-28
- Granted: 1994-09-13
- Earliest claimed: 1988-06-07
- Assignees: Dallas Semiconductor Corporation
- Inventors: Bill Podkowa
- Web page: https://patentgrep.com/patent/US5347472A

## CPC

- G04G 99/006: {Electronic time-pieces using a microcomputer, e.g. for multi-function clocks}
- G04G 3/00: Producing timing pulses (driving circuits for stepping motors G04C3/14; producing preselected time intervals for use as timing standards G04F5/00; pulse technique in general H03K; control, synchronisation, or stabilisation of generators in general H03L)
- G04G: ELECTRONIC TIME-PIECES

## Abstract

A low-power integrated circuit clock/calendar, wherein separate data busses are used for the time data and the alarm data. Conditional logic is used to only compare seconds bits (unless a match occurs, in which case higher-order bits are then compared). Thus, charging and discharging of the data busses (which carrying the time data) occurs only when a data transition is occurring. A special clocked latch circuit is used to hold the potential of each line of the time data bus constant, except when the data on the bus is actually changing. These innovations help to provide extremely long battery lifetime, since charge is not consumed by unnecessarily charging and discharging busses. Preferably this bus architecture is combined with a low-power logic architecture.

## Claims

### Claim 1

An integrated circuit, comprising:
a memory;
a sequencer;
comparison circuitry;
first and second busses, each of said busses connecting said memory to said comparison circuitry;
wherein said sequencer and said comparison circuitry are connected and programmed so that said comparison circuitry compares pending data on said first bus to pending data on said second bus, and additional data for said first bus and data for said second bus are fetched if said comparison circuitry detects a match between said pending data on said first bus and pending data on said second bus; and
a clocked latch connected between said memory and said first bus, so that said first bus is held at a constant potential except when data on said first bus is required to change.